Gabor Juhos 14fdd1a8bf MIPS: start{, 64}.S: fill branch delay slots with NOP instructions ... The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>		2013-01-22 21:09:34 +01:00
..
cpu	MIPS: start{, 64}.S: fill branch delay slots with NOP instructions	2013-01-22 21:09:34 +01:00
include/asm	MIPS: convert IO port accessor functions to 'static inline'	2013-01-22 21:07:19 +01:00
lib	MIPS: bootm.c: add support for 'prep' and 'go' subcommands	2013-01-16 10:52:07 +01:00
config.mk	MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefiles	2012-08-24 00:34:47 +02:00