14b7fba31f
Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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*/
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#ifndef _CLK_MEM_N5X_
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#define _CLK_MEM_N5X_
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/* Clock Manager registers */
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#define MEMCLKMGR_STAT 4
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#define MEMCLKMGR_INTRGEN 8
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#define MEMCLKMGR_INTRMSK 0x0c
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#define MEMCLKMGR_INTRCLR 0x10
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#define MEMCLKMGR_INTRSTS 0x14
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#define MEMCLKMGR_INTRSTK 0x18
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#define MEMCLKMGR_INTRRAW 0x1c
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/* Memory Clock Manager PPL group registers */
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#define MEMCLKMGR_MEMPLL_EN 0x20
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#define MEMCLKMGR_MEMPLL_ENS 0x24
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#define MEMCLKMGR_MEMPLL_ENR 0x28
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#define MEMCLKMGR_MEMPLL_BYPASS 0x2c
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#define MEMCLKMGR_MEMPLL_BYPASSS 0x30
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#define MEMCLKMGR_MEMPLL_BYPASSR 0x34
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#define MEMCLKMGR_MEMPLL_MEMDIV 0x38
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#define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c
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#define MEMCLKMGR_MEMPLL_PLLCTRL 0x40
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#define MEMCLKMGR_MEMPLL_PLLDIV 0x44
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#define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48
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#define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c
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#define MEMCLKMGR_CTRL_BOOTMODE BIT(0)
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#define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8)
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#define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK \
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(MEMCLKMGR_STAT_MEMPLL_LOCKED)
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#define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK BIT(0)
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#define MEMCLKMGR_INTER_MEMPLLLOST_MASK BIT(2)
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#define MEMCLKMGR_BYPASS_MEMPLL_ALL 0x1
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#define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET 0
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#define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4
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#define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8
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#define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12
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#define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK BIT(0)
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#define MEMCLKMGR_MEMDIV_DIVIDER_MASK GENMASK(1, 0)
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#define MEMCLKMGR_PLLGLOB_PSRC_MASK GENMASK(17, 16)
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#define MEMCLKMGR_PLLGLOB_PSRC_OFFSET 16
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#define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28)
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#define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
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#define MEMCLKMGR_PSRC_EOSC1 0
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#define MEMCLKMGR_PSRC_INTOSC 1
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#define MEMCLKMGR_PSRC_F2S 2
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#define MEMCLKMGR_PLLCTRL_BYPASS_MASK BIT(0)
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#define MEMCLKMGR_PLLCTRL_RST_N_MASK BIT(1)
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#define MEMCLKMGR_PLLDIV_DIVR_MASK GENMASK(5, 0)
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#define MEMCLKMGR_PLLDIV_DIVF_MASK GENMASK(16, 8)
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#define MEMCLKMGR_PLLDIV_DIVQ_MASK GENMASK(26, 24)
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#define MEMCLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
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#define MEMCLKMGR_PLLDIV_DIVR_OFFSET 0
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#define MEMCLKMGR_PLLDIV_DIVF_OFFSET 8
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#define MEMCLKMGR_PLLDIV_DIVQ_QDIV_OFFSET 24
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#define MEMCLKMGR_PLLDIV_RANGE_OFFSET 28
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#define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
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#define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
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#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7)
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#define MEMCLKMGR_EXTCNTRST_ALLCNTRST \
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(MEMCLKMGR_EXTCNTRST_C0CNTRST)
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#endif /* _CLK_MEM_N5X_ */
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