0567099bea
There are a few remaining places where we say CONFIG_SECURE_BOOT rather
than CONFIG_IMX HAB. Update these instances.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Eddy Petrișor <eddy.petrisor@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Fixes: d714a75fd4 ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
128 lines
4.3 KiB
INI
128 lines
4.3 KiB
INI
/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : sd
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*/
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BOOT_FROM sd
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/*
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* Secure boot support
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*/
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#ifdef CONFIG_IMX_HAB
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable OCRAM EPDC */
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DATA 4 0x30340004 0x4F400005
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/* =============================================================================
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* DDR Controller Registers
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* =============================================================================
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* Memory type: DDR3
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* Manufacturer: ISSI
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* Device Part Number: IS43TR16256AL-125KBL
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* Clock Freq.: 533MHz
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* Density per CS in Gb: 4
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* Chip Selects used: 1
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* Number of Banks: 8
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* Row address: 15
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* Column address: 10
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* Data bus width: 16
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* ROW-BANK interleave: ENABLED
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* =============================================================================
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*/
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DATA 4 0x30391000 0x00000002 // deassert presetn
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DATA 4 0x307A0000 0x01041001 // DDRC_MSTR
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DATA 4 0x307A0064 0x00400046 // DDRC_RFSHTMG
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DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
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DATA 4 0x307A00D4 0x00690000 // DDRC_INIT1
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DATA 4 0x307A00D0 0x00020083 // DDRC_INIT0
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DATA 4 0x307A00DC 0x09300004 // DDRC_INIT3
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DATA 4 0x307A00E0 0x04080000 // DDRC_INIT4
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DATA 4 0x307A00E4 0x00100004 // DDRC_INIT5
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DATA 4 0x307A00F4 0x0000033F // DDRC_RANKCTL
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DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
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DATA 4 0x307A0104 0x0007020D // DDRC_DRAMTMG1
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DATA 4 0x307A0108 0x03040407 // DDRC_DRAMTMG2
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DATA 4 0x307A010C 0x00002006 // DDRC_DRAMTMG3
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DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
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DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
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DATA 4 0x307A0120 0x00000803 // DDRC_DRAMTMG8
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DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
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DATA 4 0x307A0190 0x02098204 // DDRC_DFITMG0
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DATA 4 0x307A0194 0x00030303 // DDRC_DFITMG1
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DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
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DATA 4 0x307A01A4 0x00100020 // DDRC_DFIUPD1
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DATA 4 0x307A01A8 0x80100004 // DDRC_DFIUPD2
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DATA 4 0x307A0200 0x00000015 // DDRC_ADDRMAP0
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DATA 4 0x307A0204 0x00070707 // DDRC_ADDRMAP1
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DATA 4 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
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DATA 4 0x307A0214 0x06060606 // DDRC_ADDRMAP5
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DATA 4 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
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DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
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DATA 4 0x307A0244 0x00000001 // DDRC_ODTMAP
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/* =============================================================================
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* PHY Control Register
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* =============================================================================
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*/
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DATA 4 0x30391000 0x00000000 // deassert presetn
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DATA 4 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
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DATA 4 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
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DATA 4 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
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DATA 4 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
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DATA 4 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
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DATA 4 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
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DATA 4 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
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DATA 4 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
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DATA 4 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
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DATA 4 0x30790018 0x0000000F // DDR_PHY_LP_CON0
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DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
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DATA 4 0x307900C0 0x0E447304
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DATA 4 0x307900C0 0x0E447306
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DATA 4 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
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DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
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/* =============================================================================
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* Final Initialization start sequence
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* =============================================================================
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*/
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DATA 4 0x30384130 0x00000000 // Disable Clock
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DATA 4 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
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DATA 4 0x30384130 0x00000002 // Enable Clock
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/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
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