051a8ad7bb
Use different location for SPDX line. Also update dates for new mainline DTS files. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
72 lines
1.0 KiB
Plaintext
72 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 - 2015 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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model = "Zynq ZYBO Development Board";
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compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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serial0 = &uart1;
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spi0 = &qspi;
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mmc0 = &sdhci0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x20000000>;
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};
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chosen {
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bootargs = "";
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio0 46 1>;
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};
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};
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&clkc {
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ps-clk-frequency = <50000000>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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reg = <0>;
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device_type = "ethernet-phy";
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};
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};
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&qspi {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&sdhci0 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&uart1 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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};
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