u-boot/arch/arm/dts/bitmain-antminer-s9.dts
Ezequiel Garcia c66f5620e6 arm: zynq: Add support for Bitmain Antminer S9 control board
This is control board on Bitmain Antminer S9.
There are 3 board variables with 256MB, 512MB and 1024MB DDR.
DDR memory is automatically detected with using get_with using
get_ram_size().

Bitmain is using 16MB space for FPGA which is handled via
reserved-memory. Also U-Boot is allocating 16B for storing bootcounts.
Watchdog is started but never service in U-Boot.

SPL MMC is working. SPL NAND is not working because it is not supported
as of now.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00

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// SPDX-License-Identifier: GPL-2.0
/*
* Bitmain Antminer S9 board DTS
*
* Copyright (C) 2018 Michal Simek
* Copyright (C) 2018 VanguardiaSur
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
model = "Bitmain Antminer S9 Board";
compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
mmc0 = &sdhci0;
gpio0 = &gpio0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
bootcount@efffff0 {
reg = <0xefffff0 0x10>;
no-map;
};
fpga_space@f000000 {
reg = <0xf000000 0x1000000>;
no-map;
};
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
/* 0362/5e62 */
ethernet_phy: ethernet-phy@1 {
reg = <1>;
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
disable-wp;
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
&watchdog0 {
reset-on-timeout;
timeout-sec = <200>;
};