308520b8f2
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define RISCV_MMODE_TIMERBASE 0xe6000000
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#define RISCV_MMODE_TIMER_FREQ 60000000
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#define RISCV_SMODE_TIMER_FREQ 60000000
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/*
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* CPU and Board Configuration Options
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*/
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/*
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* Miscellaneous configurable options
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*/
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/*
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1 \
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(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
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#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
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#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
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/*
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* Serial console configuration
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*/
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#define CFG_SYS_NS16550_CLK 19660800
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/* Init Stack Pointer */
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/* support JEDEC */
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#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
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#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
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/* max number of memory banks */
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/*
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* There are 4 banks supported for this Controller,
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* but we have only 1 bank connected to flash on board
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*/
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#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
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/* environments */
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/* SPI FLASH */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CFG_SYS_BOOTMAPSZ (64 << 20)
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/* Increase max gunzip size */
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/* Support autoboot from RAM (kernel image is loaded via debug port) */
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#define KERNEL_IMAGE_ADDR "0x2000000 "
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#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
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"ram "
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#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
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"bootcmd_ram=" \
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"booti " \
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KERNEL_IMAGE_ADDR \
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"- $fdtcontroladdr\0"
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/* When we use RAM as ENV */
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/* Enable distro boot */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na) \
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func(RAM, ram, na)
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr_r=0x00080000\0" \
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"pxefile_addr_r=0x01f00000\0" \
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"scriptaddr=0x01f00000\0" \
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"fdt_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x02800000\0" \
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BOOTENV
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#endif /* __CONFIG_H */
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