8a897c4f97
Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
289 lines
6.7 KiB
C
289 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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* Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
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* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
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* Copyright (C) 2019 DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <power/tps65910.h>
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#include <jffs2/load_kernel.h>
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#include <mtd_node.h>
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#include <fdt_support.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* DDR RAM defines */
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#if defined(CONFIG_TARGET_PCM051)
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#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
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#else
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#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
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#endif
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#define OSC (V_OSCK / 1000000)
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const struct dpll_params dpll_ddr = {
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DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr;
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}
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = 0x18B,
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.cm1ioctl = 0x18B,
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.cm2ioctl = 0x18B,
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.dt0ioctl = 0x18B,
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.dt1ioctl = 0x18B,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = 0x80,
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.cmd0iclkout = 0x0,
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.cmd1csratio = 0x80,
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.cmd1iclkout = 0x0,
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.cmd2csratio = 0x80,
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.cmd2iclkout = 0x0,
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};
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enum {
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PHYCORE_R2_MT41K128M16JT_256MB,
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PHYCORE_R2_MT41K256M16TW107IT_512MB,
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PHYCORE_R2_MT41K512M16HA125IT_1024MB,
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PHYCORE_R13_MT41K256M16HA125E_256MB,
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};
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struct am335x_sdram_timings {
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struct emif_regs ddr3_emif_reg_data;
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struct ddr_data ddr3_data;
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};
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static struct am335x_sdram_timings physom_timings[] = {
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[PHYCORE_R2_MT41K128M16JT_256MB] = {
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.ddr3_emif_reg_data = {
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.sdram_config = 0x61C052B2,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0x0AAAD4DB,
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.sdram_tim2 = 0x26437FDA,
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.sdram_tim3 = 0x501F83FF,
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.zq_config = 0x50074BE4,
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.emif_ddr_phy_ctlr_1 = 0x7,
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.ocp_config = 0x003d3d3d,
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},
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.ddr3_data = {
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.datardsratio0 = 0x36,
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.datawdsratio0 = 0x38,
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.datafwsratio0 = 0x99,
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.datawrsratio0 = 0x73,
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},
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},
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[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
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.ddr3_emif_reg_data = {
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.sdram_config = 0x61C05332,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0x0AAAD4DB,
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.sdram_tim2 = 0x266B7FDA,
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.sdram_tim3 = 0x501F867F,
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.zq_config = 0x50074BE4,
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.emif_ddr_phy_ctlr_1 = 0x7,
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.ocp_config = 0x003d3d3d,
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},
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.ddr3_data = {
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.datardsratio0 = 0x37,
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.datawdsratio0 = 0x38,
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.datafwsratio0 = 0x92,
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.datawrsratio0 = 0x72,
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},
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},
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[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
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.ddr3_emif_reg_data = {
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.sdram_config = 0x61C053B2,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0x0AAAD4DB,
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.sdram_tim2 = 0x268F7FDA,
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.sdram_tim3 = 0x501F88BF,
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.zq_config = 0x50074BE4,
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.emif_ddr_phy_ctlr_1 = 0x7,
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.ocp_config = 0x003d3d3d,
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},
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.ddr3_data = {
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.datardsratio0 = 0x38,
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.datawdsratio0 = 0x4d,
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.datafwsratio0 = 0x9d,
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.datawrsratio0 = 0x82,
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},
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},
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[PHYCORE_R13_MT41K256M16HA125E_256MB] = {
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.ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN,
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},
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.ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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},
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},
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};
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void sdram_init(void)
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{
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#if defined(CONFIG_TARGET_PCM051)
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int ram_type_index = PHYCORE_R13_MT41K256M16HA125E_256MB;
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#else
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/* Configure memory to maximum supported size for detection */
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int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
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config_ddr(DDR_CLK_MHZ, &ioregs,
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&physom_timings[ram_type_index].ddr3_data,
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&ddr3_cmd_ctrl_data,
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&physom_timings[ram_type_index].ddr3_emif_reg_data,
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0);
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/* Detect memory physically present */
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
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CFG_MAX_RAM_BANK_SIZE);
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/* Reconfigure memory for actual detected size */
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switch (gd->ram_size) {
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case SZ_1G:
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ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
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break;
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case SZ_512M:
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ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
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break;
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case SZ_256M:
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default:
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ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
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break;
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}
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#endif
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config_ddr(DDR_CLK_MHZ, &ioregs,
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&physom_timings[ram_type_index].ddr3_data,
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&ddr3_cmd_ctrl_data,
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&physom_timings[ram_type_index].ddr3_emif_reg_data,
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0);
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}
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const struct dpll_params *get_dpll_mpu_params(void)
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{
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int ind = get_sys_clk_index();
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int freq = am335x_get_efuse_mpu_max_freq(cdev);
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switch (freq) {
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case MPUPLL_M_1000:
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return &dpll_mpu_opp[ind][5];
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case MPUPLL_M_800:
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return &dpll_mpu_opp[ind][4];
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case MPUPLL_M_720:
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return &dpll_mpu_opp[ind][3];
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case MPUPLL_M_600:
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return &dpll_mpu_opp[ind][2];
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case MPUPLL_M_500:
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return &dpll_mpu_opp100;
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case MPUPLL_M_300:
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return &dpll_mpu_opp[ind][0];
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}
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return &dpll_mpu_opp[ind][0];
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}
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static void scale_vcores_generic(int freq)
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{
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int sil_rev, mpu_vdd;
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/*
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* We use a TPS65910 PMIC. For all MPU frequencies we support we use a
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* CORE voltage of 1.10V. For MPU voltage we need to switch based on
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* the frequency we are running at.
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*/
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if (power_tps65910_init(0))
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return;
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/*
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* Depending on MPU clock and PG we will need a different
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* VDD to drive at that speed.
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*/
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sil_rev = readl(&cdev->deviceid) >> 28;
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mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
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/* Tell the TPS65910 to use i2c */
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tps65910_set_i2c_control();
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/* First update MPU voltage. */
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if (tps65910_voltage_update(MPU, mpu_vdd))
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return;
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/* Second, update the CORE voltage. */
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if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
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return;
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}
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void scale_vcores(void)
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{
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int freq;
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freq = am335x_get_efuse_mpu_max_freq(cdev);
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scale_vcores_generic(freq);
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_i2c0_pin_mux();
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enable_board_pin_mux();
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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static const struct node_info nodes[] = {
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{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
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};
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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#endif
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return 0;
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}
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#endif
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