9973e3c614
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
604 lines
19 KiB
C
604 lines
19 KiB
C
/*
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* (C) Copyright 2001, 2002
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* Dave Ellis, SIXNET, dge@sixnetio.com.
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* Based on code by:
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* and other contributors to U-Boot. See file CREDITS for list
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* of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <jffs2/jffs2.h>
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#include <mpc8xx.h>
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#include <net.h> /* for eth_init() */
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#include <rtc.h>
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#include "sixnet.h"
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#ifdef CONFIG_SHOW_BOOT_PROGRESS
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# include <status_led.h>
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#endif
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#if defined(CONFIG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define ORMASK(size) ((-size) & OR_AM_MSK)
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static long ram_size(ulong *, long);
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_SHOW_BOOT_PROGRESS
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void show_boot_progress (int status)
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{
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#if defined(CONFIG_STATUS_LED)
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# if defined(STATUS_LED_BOOT)
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if (status == 15) {
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/* ready to transfer to kernel, make sure LED is proper state */
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status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
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}
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# endif /* STATUS_LED_BOOT */
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#endif /* CONFIG_STATUS_LED */
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}
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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* returns 0 if recognized, -1 if unknown
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*/
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int checkboard (void)
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{
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puts ("Board: SIXNET SXNI855T\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_CMD_PCMCIA)
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#error "SXNI855T has no PCMCIA port"
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#endif
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/* ------------------------------------------------------------------------- */
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#define _not_used_ 0xffffffff
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/* UPMB table for dual UART. */
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/* this table is for 50MHz operation, it should work at all lower speeds */
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const uint duart_table[] =
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{
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/* single read. (offset 0 in upm RAM) */
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0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
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0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
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/* burst read. (offset 8 in upm RAM) */
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* single write. (offset 18 in upm RAM) */
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0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
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0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
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/* burst write. (offset 20 in upm RAM) */
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* refresh. (offset 30 in upm RAM) */
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* exception. (offset 3c in upm RAM) */
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_not_used_, _not_used_, _not_used_, _not_used_,
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};
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/* Load FPGA very early in boot sequence, since it must be
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* loaded before the 16C2550 serial channels can be used as
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* console channels.
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*
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* Note: Much of the configuration is not complete. The
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* stack is in DPRAM since SDRAM has not been initialized,
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* so the stack must be kept small. Global variables
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* are still in FLASH, so they cannot be written.
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* Only the FLASH, DPRAM, immap and FPGA can be addressed,
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* the other chip selects may not have been initialized.
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* The clocks have been initialized, so udelay() can be
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* used.
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*/
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#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
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#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
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#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
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#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
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int board_postclk_init (void)
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{
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/* the data to load to the XCSxxXL FPGA */
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static const unsigned char fpgadata[] = {
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# include "fpgadata.c"
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};
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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#define porta (immap->im_ioport.iop_padat)
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const unsigned char* pdata;
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/* /INITFPGA and DONEFPGA signals are inputs */
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immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
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/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
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porta &= ~FPGA_PROGRAM_L;
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/* Set FPGA as an output */
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immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
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/* delay a little to make sure FPGA sees it, really
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* only need less than a microsecond.
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*/
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udelay(10);
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/* unassert /PROGRAM */
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porta |= FPGA_PROGRAM_L;
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/* delay while FPGA does last erase, indicated by
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* /INITFPGA going high. This should happen within a
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* few milliseconds.
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*/
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/* ### FIXME - a timeout check would be good, maybe flash
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* the status LED to indicate the error?
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*/
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while ((porta & FPGA_INIT_L) == 0)
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; /* waiting */
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/* write program data to FPGA at the programming address
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* so extra /CS1 strobes at end of configuration don't actually
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* write to any registers.
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*/
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fpga = 0xff; /* first write is ignored */
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fpga = 0xff; /* fill byte */
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fpga = 0xff; /* fill byte */
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fpga = 0x4f; /* preamble code */
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fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
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fpga = 0x4b; /* field check code */
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pdata = fpgadata;
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/* while no error write out each of the 28 byte frames */
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while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
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&& pdata < fpgadata + sizeof(fpgadata)) {
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fpga = 0x4f; /* preamble code */
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/* 21 bytes of data in a frame */
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++); fpga = *(pdata++);
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fpga = *(pdata++);
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fpga = 0x4b; /* field check code */
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fpga = 0xff; /* extended write cycle */
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fpga = 0x4b; /* extended write cycle
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* (actually 0x4b from bitgen.exe)
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*/
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fpga = 0xff; /* extended write cycle */
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fpga = 0xff; /* extended write cycle */
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fpga = 0xff; /* extended write cycle */
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}
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fpga = 0xff; /* startup byte */
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fpga = 0xff; /* startup byte */
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fpga = 0xff; /* startup byte */
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fpga = 0xff; /* startup byte */
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#if 0 /* ### FIXME */
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/* If didn't load all the data or FPGA_DONE is low the load failed.
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* Maybe someday stop here and flash the status LED? The console
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* is not configured, so can't print an error message. Can't write
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* global variables to set a flag (except gd?).
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* For now it must work.
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*/
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#endif
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/* Now that the FPGA is loaded, set up the Dual UART chip
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* selects. Must be done here since it may be used as the console.
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*/
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upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
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memctl->memc_mbmr = DUART_MBMR;
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memctl->memc_or5 = DUART_OR_VALUE;
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memctl->memc_br5 = DUART_BR5_VALUE;
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memctl->memc_or6 = DUART_OR_VALUE;
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memctl->memc_br6 = DUART_BR6_VALUE;
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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/* base address for SRAM, assume 32-bit port, valid */
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#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
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/* up to 64MB - will be adjusted for actual size */
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#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
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| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
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/*
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* Miscellaneous platform dependent initializations after running in RAM.
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*/
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int misc_init_r (void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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char* s;
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char* e;
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int reg;
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bd_t *bd = gd->bd;
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memctl->memc_or2 = NVRAM_OR_PRELIM;
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memctl->memc_br2 = NVRAM_BR_VALUE;
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/* Is there any SRAM? Is it 16 or 32 bits wide? */
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/* First look for 32-bit SRAM */
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bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
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if (bd->bi_sramsize == 0) {
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/* no 32-bit SRAM, but there could be 16-bit SRAM since
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* it would report size 0 when configured for 32-bit bus.
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* Try again with a 16-bit bus.
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*/
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memctl->memc_br2 |= BR_PS_16;
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bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
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}
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if (bd->bi_sramsize == 0) {
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memctl->memc_br2 = 0; /* disable select since nothing there */
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}
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else {
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/* adjust or2 for actual size of SRAM */
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memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
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bd->bi_sramstart = CFG_SRAM_BASE;
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printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
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}
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/* set standard MPC8xx clock so kernel will see the time
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* even if it doesn't have a DS1306 clock driver.
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* This helps with experimenting with standard kernels.
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*/
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{
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ulong tim;
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struct rtc_time tmp;
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rtc_get(&tmp); /* get time from DS1306 RTC */
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/* convert to seconds since 1970 */
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tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
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tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
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immap->im_sitk.sitk_rtck = KAPWR_KEY;
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immap->im_sit.sit_rtc = tim;
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}
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/* set up ethernet address for SCC ethernet. If eth1addr
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* is present it gets a unique address, otherwise it
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* shares the FEC address.
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*/
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s = getenv("eth1addr");
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if (s == NULL)
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s = getenv("ethaddr");
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for (reg=0; reg<6; ++reg) {
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bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
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if (s)
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s = (*e) ? e+1 : e;
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}
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return (0);
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}
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#if defined(CONFIG_CMD_NAND)
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void nand_init(void)
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{
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unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
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printf ("%4lu MB\n", totlen >> 20);
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}
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*
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* The memory size MUST be a power of 2 for this to work.
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*
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* The only memory modified is 8 bytes at offset 0. This is important
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* since for the SRAM this location is reserved for autosizing, so if
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* it is modified and the board is reset before ram_size() completes
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* no damage is done. Normally even the memory at 0 is preserved. The
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* higher SRAM addresses may contain battery backed RAM disk data which
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* must never be corrupted.
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*/
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static long ram_size(ulong *base, long maxsize)
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{
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volatile long *test_addr;
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volatile ulong *base_addr = base;
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ulong ofs; /* byte offset from base_addr */
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ulong save; /* to make test non-destructive */
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ulong save2; /* to make test non-destructive */
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long ramsize = -1; /* size not determined yet */
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save = *base_addr; /* save value at 0 so can restore */
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save2 = *(base_addr+1); /* save value at 4 so can restore */
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/* is any SRAM present? */
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*base_addr = 0x5555aaaa;
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/* It is important to drive the data bus with different data so
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* it doesn't remember the value and look like RAM that isn't there.
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*/
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*(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
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if (*base_addr != 0x5555aaaa)
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ramsize = 0; /* no RAM present, or defective */
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else {
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*base_addr = 0xaaaa5555;
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*(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
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if (*base_addr != 0xaaaa5555)
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ramsize = 0; /* no RAM present, or defective */
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}
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/* now size it if any is present */
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for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
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test_addr = (long*)((long)base_addr + ofs); /* location to test */
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*base_addr = ~*test_addr;
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if (*base_addr == *test_addr)
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ramsize = ofs; /* wrapped back to 0, so this is the size */
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}
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*base_addr = save; /* restore value at 0 */
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*(base_addr+1) = save2; /* restore value at 4 */
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return (ramsize);
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}
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/* ------------------------------------------------------------------------- */
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/* sdram table based on the FADS manual */
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/* for chip MB811171622A-100 */
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/* this table is for 50MHz operation, it should work at all lower speeds */
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const uint sdram_table[] =
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{
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/* single read. (offset 0 in upm RAM) */
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0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
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0x1ff77c47,
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/* precharge and Mode Register Set initialization (offset 5).
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* This is also entered at offset 6 to do Mode Register Set
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* without the precharge.
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*/
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0x1ff77c34, 0xefeabc34, 0x1fb57c35,
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/* burst read. (offset 8 in upm RAM) */
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0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* single write. (offset 18 in upm RAM) */
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/* FADS had 0x1f27fc04, ...
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* but most other boards have 0x1f07fc04, which
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* sets GPL0 from A11MPC to 0 1/4 clock earlier,
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* like the single read.
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* This seems better so I am going with the change.
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*/
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0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* burst write. (offset 20 in upm RAM) */
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0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* refresh. (offset 30 in upm RAM) */
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* exception. (offset 3c in upm RAM) */
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0x7ffffc07, _not_used_, _not_used_, _not_used_ };
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/* ------------------------------------------------------------------------- */
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#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
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/* precharge and set Mode Register */
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#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
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MCR_MB_CS3 | /* chip select */ \
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MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
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/* set Mode Register, no precharge */
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#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
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MCR_MB_CS3 | /* chip select */ \
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MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
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/* runs refresh loop twice so get 8 refresh cycles */
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#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
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MCR_MB_CS3 | /* chip select */ \
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MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
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/* MAMR values work in either mamr or mbmr */
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#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
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((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
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| MAMR_DSA_1_CYCL /* 1 cycle disable */ \
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| MAMR_RLFA_1X /* Read loop 1 time */ \
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| MAMR_WLFA_1X /* Write loop 1 time */ \
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| MAMR_TLFA_4X) /* Timer loop 4 times */
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/* 8 column SDRAM */
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#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
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| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
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| MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
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/* 9 column SDRAM */
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#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
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| MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
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| MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
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/* base address 0, 32-bit port, SDRAM UPM, valid */
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#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
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/* up to 256MB, SAM, G5LS - will be adjusted for actual size */
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#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
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/* This is the Mode Select Register value for the SDRAM.
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* Burst length: 4
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* Burst Type: sequential
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* CAS Latency: 2
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* Write Burst Length: burst
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*/
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#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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uint size_sdram = 0;
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uint size_sdram9 = 0;
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uint base = 0; /* SDRAM must start at 0 */
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int i;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/* Configure the refresh (mostly). This needs to be
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* based upon processor clock speed and optimized to provide
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* the highest level of performance.
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*
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* Preliminary prescaler for refresh.
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* This value is selected for four cycles in 31.2 us,
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* which gives 8192 cycles in 64 milliseconds.
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* This may be too fast, but works for any memory.
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* It is adjusted to 4096 cycles in 64 milliseconds if
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* possible once we know what memory we have.
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*
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* We have to be careful changing UPM registers after we
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* ask it to run these commands.
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*
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* PTA - periodic timer period for our design is
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* 50 MHz x 31.2us
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* --------------- = 195
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* 1 x 8 x 1
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*
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* 50MHz clock
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* 31.2us refresh interval
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* SCCR[DFBRG] 0
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* PTP divide by 8
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* 1 chip select
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*/
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memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
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memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
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/* The SDRAM Mode Register value is shifted left 2 bits since
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* A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
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*/
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memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
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udelay(200); /* SDRAM needs 200uS before set it up */
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/* Now run the precharge/nop/mrs commands. */
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memctl->memc_mcr = SDRAM_MCR_PRE;
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udelay(2);
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/* Run 8 refresh cycles (2 sets of 4) */
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memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
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udelay(2);
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/* some brands want Mode Register set after the refresh
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* cycles. This shouldn't hurt anything for the brands
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* that were happy with the first time we set it.
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*/
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memctl->memc_mcr = SDRAM_MCR_MRS;
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udelay(2);
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memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
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memctl->memc_or3 = SDRAM_OR_PRELIM;
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memctl->memc_br3 = SDRAM_BR_VALUE + base;
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/* Some brands need at least 10 DRAM accesses to stabilize.
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* It wont hurt the brands that don't.
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*/
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for (i=0; i<10; ++i) {
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volatile ulong *addr = (volatile ulong *)base;
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ulong val;
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val = *(addr + i);
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*(addr + i) = val;
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}
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/* Check SDRAM memory Size in 8 column mode.
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* For a 9 column memory we will get half the actual size.
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*/
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size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
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/* Check SDRAM memory Size in 9 column mode.
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* For an 8 column memory we will see at most 4 megabytes.
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*/
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memctl->memc_mamr = SDRAM_MAMR_9COL;
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size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
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if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
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size_sdram = size_sdram9;
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else /* go back to 8 columns */
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memctl->memc_mamr = SDRAM_MAMR_8COL;
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/* adjust or3 for actual size of SDRAM
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*/
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memctl->memc_or3 |= ORMASK(size_sdram);
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/* Adjust refresh rate depending on SDRAM type.
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* For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
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* it at the current (fast) rate.
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* For 16, 64 and 128 MBit half the rate will do.
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*/
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if (size_sdram <= 32 * 1024 * 1024)
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memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */
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return (size_sdram);
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}
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