0dc78ff857
Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| cpu | ||
| dts | ||
| include/asm | ||
| lib | ||
| config.mk | ||
| Kconfig | ||
| Makefile | ||