15c41a8d9e
The PMIC on Apalis iMX6 may have ECC errors in fuses that will prevent correct settings. Up to one bit error per fuse bank may be reported and corrected by the ECC logic. Two bit errors can only be reported. Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
108 lines
3.7 KiB
C
108 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014-2019, Toradex AG
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*/
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/*
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* Helpers for Freescale PMIC PF0100
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*/
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#ifndef PF0100_H_
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#define PF0100_H_
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/* bit definitions */
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#define PFUZE100_BIT_0 (0x01 << 0)
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#define PFUZE100_BIT_1 (0x01 << 1)
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#define PFUZE100_BIT_2 (0x01 << 2)
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#define PFUZE100_BIT_3 (0x01 << 3)
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#define PFUZE100_BIT_4 (0x01 << 4)
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#define PFUZE100_BIT_5 (0x01 << 5)
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#define PFUZE100_BIT_6 (0x01 << 6)
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#define PFUZE100_BIT_7 (0x01 << 7)
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/* 7-bit I2C bus slave address */
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#define PFUZE100_I2C_ADDR (0x08)
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/* Register Addresses */
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#define PFUZE100_DEVICEID (0x0)
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#define PFUZE100_REVID (0x3)
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#define PFUZE100_INTSTAT3 (0xe)
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#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7
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#define PFUZE100_SW1AMODE (0x23)
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#define PFUZE100_SW1ACON 36
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#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
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#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
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#define PFUZE100_SW1CCON 49
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#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
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#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
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#define PFUZE100_SW1AVOL 32
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#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
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#define PFUZE100_SW1CVOL 46
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#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
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#define PFUZE100_VGEN1CTL (0x6c)
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#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
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#define PFUZE100_SWBSTCTL (0x66)
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/* Always ON, Auto Switching Mode, 5.0V */
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#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
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/* chooses the extended page (registers 0x80..0xff) */
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#define PFUZE100_PAGE_REGISTER 0x7f
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#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
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#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
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#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
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/* extended page 1 */
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#define PFUZE100_OTP_ECC_SE1 0x8a
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#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0
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#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1
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#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2
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#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3
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#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4
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#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \
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(PFUZE100_BIT_ECC2_SE) | \
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(PFUZE100_BIT_ECC3_SE) | \
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(PFUZE100_BIT_ECC4_SE) | \
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(PFUZE100_BIT_ECC5_SE))
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#define PFUZE100_OTP_ECC_SE2 0x8b
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#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0
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#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1
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#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2
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#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3
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#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4
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#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \
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(PFUZE100_BIT_ECC7_SE) | \
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(PFUZE100_BIT_ECC8_SE) | \
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(PFUZE100_BIT_ECC9_SE) | \
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(PFUZE100_BIT_ECC10_SE))
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#define PFUZE100_OTP_ECC_DE1 0x8c
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#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0
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#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1
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#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2
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#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3
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#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4
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#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \
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(PFUZE100_BIT_ECC2_DE) | \
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(PFUZE100_BIT_ECC3_DE) | \
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(PFUZE100_BIT_ECC4_DE) | \
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(PFUZE100_BIT_ECC5_DE))
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#define PFUZE100_OTP_ECC_DE2 0x8d
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#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0
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#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1
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#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2
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#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3
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#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4
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#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \
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(PFUZE100_BIT_ECC7_DE) | \
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(PFUZE100_BIT_ECC8_DE) | \
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(PFUZE100_BIT_ECC9_DE) | \
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(PFUZE100_BIT_ECC10_DE))
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#define PFUZE100_FUSE_POR1 0xe4
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#define PFUZE100_FUSE_POR2 0xe5
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#define PFUZE100_FUSE_POR3 0xe6
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#define PFUZE100_FUSE_POR_M (0x1 << 1)
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/* output some informational messages, return the number FUSE_POR=1 */
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/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
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unsigned pmic_init(void);
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#endif /* PF0100_H_ */
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