bf9e3b38f7
* Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems
448 lines
9.2 KiB
C
448 lines
9.2 KiB
C
/*
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* MCF5272 Internal Memory Map
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*
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* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5272__
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#define __IMMAP_5272__
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/* System configuration registers
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*/
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typedef struct sys_ctrl {
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uint sc_mbar;
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ushort sc_scr;
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ushort sc_spr;
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uint sc_pmr;
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char res1[2];
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ushort sc_alpr;
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uint sc_dir;
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char res2[12];
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} sysctrl_t;
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/* Interrupt module registers
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*/
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typedef struct int_ctrl {
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uint int_icr1;
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uint int_icr2;
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uint int_icr3;
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uint int_icr4;
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uint int_isr;
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uint int_pitr;
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uint int_piwr;
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uchar res1[3];
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uchar int_pivr;
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} intctrl_t;
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/* Chip select module registers.
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*/
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typedef struct cs_ctlr {
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uint cs_br0;
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uint cs_or0;
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uint cs_br1;
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uint cs_or1;
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uint cs_br2;
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uint cs_or2;
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uint cs_br3;
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uint cs_or3;
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uint cs_br4;
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uint cs_or4;
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uint cs_br5;
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uint cs_or5;
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uint cs_br6;
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uint cs_or6;
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uint cs_br7;
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uint cs_or7;
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} csctrl_t;
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/* GPIO port registers
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*/
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typedef struct gpio_ctrl {
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uint gpio_pacnt;
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ushort gpio_paddr;
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ushort gpio_padat;
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uint gpio_pbcnt;
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ushort gpio_pbddr;
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ushort gpio_pbdat;
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uchar res1[4];
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ushort gpio_pcddr;
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ushort gpio_pcdat;
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uint gpio_pdcnt;
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uchar res2[4];
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} gpio_t;
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/* QSPI module registers
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*/
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typedef struct qspi_ctrl {
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ushort qspi_qmr;
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uchar res1[2];
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ushort qspi_qdlyr;
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uchar res2[2];
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ushort qspi_qwr;
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uchar res3[2];
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ushort qspi_qir;
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uchar res4[2];
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ushort qspi_qar;
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uchar res5[2];
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ushort qspi_qdr;
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uchar res6[10];
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} qspi_t;
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/* PWM module registers
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*/
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typedef struct pwm_ctrl {
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uchar pwm_pwcr0;
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uchar res1[3];
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uchar pwm_pwcr1;
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uchar res2[3];
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uchar pwm_pwcr2;
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uchar res3[7];
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uchar pwm_pwwd0;
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uchar res4[3];
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uchar pwm_pwwd1;
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uchar res5[3];
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uchar pwm_pwwd2;
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uchar res6[7];
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} pwm_t;
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/* DMA module registers
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*/
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typedef struct dma_ctrl {
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ulong dma_dmr;
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uchar res1[2];
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ushort dma_dir;
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ulong dma_dbcr;
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ulong dma_dsar;
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ulong dma_ddar;
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uchar res2[12];
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} dma_t;
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/* UART module registers
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*/
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typedef struct uart_ctrl {
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uchar uart_umr;
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uchar res1[3];
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uchar uart_usr_ucsr;
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uchar res2[3];
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uchar uart_ucr;
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uchar res3[3];
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uchar uart_urb_utb;
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uchar res4[3];
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uchar uart_uipcr_uacr;
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uchar res5[3];
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uchar uart_uisr_uimr;
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uchar res6[3];
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uchar uart_udu;
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uchar res7[3];
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uchar uart_udl;
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uchar res8[3];
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uchar uart_uabu;
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uchar res9[3];
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uchar uart_uabl;
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uchar res10[3];
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uchar uart_utf;
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uchar res11[3];
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uchar uart_urf;
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uchar res12[3];
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uchar uart_ufpd;
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uchar res13[3];
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uchar uart_uip;
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uchar res14[3];
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uchar uart_uop1;
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uchar res15[3];
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uchar uart_uop0;
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uchar res16[3];
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} uart_t;
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/* SDRAM controller registers, offset: 0x180
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*/
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typedef struct sdram_ctrl {
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uchar res1[2];
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ushort sdram_sdcr;
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uchar res2[2];
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ushort sdram_sdtr;
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uchar res3[120];
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} sdramctrl_t;
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/* Timer module registers
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*/
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typedef struct timer_ctrl {
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ushort timer_tmr;
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ushort res1;
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ushort timer_trr;
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ushort res2;
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ushort timer_tcap;
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ushort res3;
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ushort timer_tcn;
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ushort res4;
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ushort timer_ter;
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uchar res5[14];
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} timer_t;
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/* Watchdog registers
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*/
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typedef struct wdog_ctrl {
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ushort wdog_wrrr;
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ushort res1;
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ushort wdog_wirr;
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ushort res2;
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ushort wdog_wcr;
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ushort res3;
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ushort wdog_wer;
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uchar res4[114];
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} wdog_t;
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/* PLIC module registers
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*/
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typedef struct plic_ctrl {
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ulong plic_p0b1rr;
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ulong plic_p1b1rr;
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ulong plic_p2b1rr;
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ulong plic_p3b1rr;
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ulong plic_p0b2rr;
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ulong plic_p1b2rr;
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ulong plic_p2b2rr;
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ulong plic_p3b2rr;
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uchar plic_p0drr;
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uchar plic_p1drr;
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uchar plic_p2drr;
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uchar plic_p3drr;
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uchar res1[4];
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ulong plic_p0b1tr;
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ulong plic_p1b1tr;
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ulong plic_p2b1tr;
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ulong plic_p3b1tr;
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ulong plic_p0b2tr;
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ulong plic_p1b2tr;
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ulong plic_p2b2tr;
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ulong plic_p3b2tr;
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uchar plic_p0dtr;
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uchar plic_p1dtr;
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uchar plic_p2dtr;
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uchar plic_p3dtr;
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uchar res2[4];
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ushort plic_p0cr;
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ushort plic_p1cr;
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ushort plic_p2cr;
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ushort plic_p3cr;
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ushort plic_p0icr;
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ushort plic_p1icr;
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ushort plic_p2icr;
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ushort plic_p3icr;
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ushort plic_p0gmr;
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ushort plic_p1gmr;
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ushort plic_p2gmr;
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ushort plic_p3gmr;
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ushort plic_p0gmt;
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ushort plic_p1gmt;
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ushort plic_p2gmt;
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ushort plic_p3gmt;
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uchar res3;
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uchar plic_pgmts;
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uchar plic_pgmta;
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uchar res4;
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uchar plic_p0gcir;
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uchar plic_p1gcir;
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uchar plic_p2gcir;
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uchar plic_p3gcir;
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uchar plic_p0gcit;
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uchar plic_p1gcit;
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uchar plic_p2gcit;
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uchar plic_p3gcit;
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uchar res5[3];
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uchar plic_pgcitsr;
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uchar res6[3];
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uchar plic_pdcsr;
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ushort plic_p0psr;
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ushort plic_p1psr;
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ushort plic_p2psr;
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ushort plic_p3psr;
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ushort plic_pasr;
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uchar res7;
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uchar plic_plcr;
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ushort res8;
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ushort plic_pdrqr;
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ushort plic_p0sdr;
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ushort plic_p1sdr;
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ushort plic_p2sdr;
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ushort plic_p3sdr;
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ushort res9;
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ushort plic_pcsr;
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uchar res10[1184];
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} plic_t;
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/* Fast ethernet controller registers
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*/
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typedef struct fec {
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uint fec_ecntrl; /* ethernet control register */
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uint fec_ievent; /* interrupt event register */
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uint fec_imask; /* interrupt mask register */
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uint fec_ivec; /* interrupt level and vector status */
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uint fec_r_des_active; /* Rx ring updated flag */
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uint fec_x_des_active; /* Tx ring updated flag */
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uint res3[10]; /* reserved */
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uint fec_mii_data; /* MII data register */
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uint fec_mii_speed; /* MII speed control register */
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uint res4[17]; /* reserved */
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uint fec_r_bound; /* end of RAM (read-only) */
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uint fec_r_fstart; /* Rx FIFO start address */
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uint res5[6]; /* reserved */
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uint fec_x_fstart; /* Tx FIFO start address */
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uint res7[21]; /* reserved */
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uint fec_r_cntrl; /* Rx control register */
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uint fec_r_hash; /* Rx hash register */
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uint res8[14]; /* reserved */
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uint fec_x_cntrl; /* Tx control register */
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uint res9[0x9e]; /* reserved */
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uint fec_addr_low; /* lower 32 bits of station address */
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uint fec_addr_high; /* upper 16 bits of station address */
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uint fec_hash_table_high; /* upper 32-bits of hash table */
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uint fec_hash_table_low; /* lower 32-bits of hash table */
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uint fec_r_des_start; /* beginning of Rx descriptor ring */
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uint fec_x_des_start; /* beginning of Tx descriptor ring */
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uint fec_r_buff_size; /* Rx buffer size */
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uint res2[9]; /* reserved */
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uchar fec_fifo[960]; /* fifo RAM */
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} fec_t;
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/* USB module registers
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*/
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typedef struct usb {
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ushort res1;
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ushort usb_fnr;
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ushort res2;
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ushort usb_fnmr;
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ushort res3;
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ushort usb_rfmr;
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ushort res4;
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ushort usb_rfmmr;
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uchar res5[3];
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uchar usb_far;
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ulong usb_asr;
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ulong usb_drr1;
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ulong usb_drr2;
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ushort res6;
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ushort usb_specr;
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ushort res7;
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ushort usb_ep0sr;
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ulong usb_iep0cfg;
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ulong usb_oep0cfg;
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ulong usb_ep1cfg;
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ulong usb_ep2cfg;
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ulong usb_ep3cfg;
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ulong usb_ep4cfg;
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ulong usb_ep5cfg;
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ulong usb_ep6cfg;
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ulong usb_ep7cfg;
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ulong usb_ep0ctl;
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ushort res8;
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ushort usb_ep1ctl;
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ushort res9;
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ushort usb_ep2ctl;
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ushort res10;
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ushort usb_ep3ctl;
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ushort res11;
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ushort usb_ep4ctl;
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ushort res12;
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ushort usb_ep5ctl;
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ushort res13;
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ushort usb_ep6ctl;
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ushort res14;
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ushort usb_ep7ctl;
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ulong usb_ep0isr;
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ushort res15;
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ushort usb_ep1isr;
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ushort res16;
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ushort usb_ep2isr;
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ushort res17;
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ushort usb_ep3isr;
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ushort res18;
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ushort usb_ep4isr;
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ushort res19;
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ushort usb_ep5isr;
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ushort res20;
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ushort usb_ep6isr;
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ushort res21;
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ushort usb_ep7isr;
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ulong usb_ep0imr;
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ushort res22;
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ushort usb_ep1imr;
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ushort res23;
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ushort usb_ep2imr;
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ushort res24;
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ushort usb_ep3imr;
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ushort res25;
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ushort usb_ep4imr;
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ushort res26;
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ushort usb_ep5imr;
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ushort res27;
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ushort usb_ep6imr;
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ushort res28;
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ushort usb_ep7imr;
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ulong usb_ep0dr;
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ulong usb_ep1dr;
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ulong usb_ep2dr;
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ulong usb_ep3dr;
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ulong usb_ep4dr;
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ulong usb_ep5dr;
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ulong usb_ep6dr;
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ulong usb_ep7dr;
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ushort res29;
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ushort usb_ep0dpr;
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ushort res30;
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ushort usb_ep1dpr;
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ushort res31;
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ushort usb_ep2dpr;
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ushort res32;
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ushort usb_ep3dpr;
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ushort res33;
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ushort usb_ep4dpr;
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ushort res34;
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ushort usb_ep5dpr;
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ushort res35;
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ushort usb_ep6dpr;
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ushort res36;
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ushort usb_ep7dpr;
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uchar res37[788];
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uchar usb_cfgram[1024];
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} usb_t;
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/* Internal memory map.
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*/
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typedef struct immap {
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sysctrl_t sysctrl_reg; /* System configuration registers */
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intctrl_t intctrl_reg; /* Interrupt controller registers */
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csctrl_t csctrl_reg; /* Chip select controller registers */
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gpio_t gpio_reg; /* GPIO controller registers */
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qspi_t qspi_reg; /* QSPI controller registers */
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pwm_t pwm_reg; /* Pulse width modulation registers */
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dma_t dma_reg; /* DMA registers */
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uart_t uart_reg[2]; /* UART registers */
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sdramctrl_t sdram_reg; /* SDRAM controller registers */
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timer_t timer_reg[4]; /* Timer registers */
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wdog_t wdog_reg; /* Watchdog registers */
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plic_t plic_reg; /* Physical layer interface registers */
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fec_t fec_reg; /* Fast ethernet controller registers */
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usb_t usb_reg; /* USB controller registers */
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} immap_t;
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#endif /* __IMMAP_5272__ */
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