516 lines
16 KiB
C
516 lines
16 KiB
C
/*
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* (C) Copyright 2001
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* Stuart Hughes <stuarth@lineo.com>
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* This file is based on similar values for other boards found in other
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* U-Boot config files, and some that I found in the mpc8260ads manual.
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*
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* Note: my board is a PILOT rev.
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* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
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*
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* (C) Copyright 2003-2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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* Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
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* Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
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* Ported to MPC8272ADS board.
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*
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* Copyright (c) 2005 MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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* Added support for PCI bridge on MPC8272ADS
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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/*
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* Figure out if we are booting low via flash HRCW or high via the BCSR.
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*/
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#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
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# define CFG_LOWBOOT 1
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#endif
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/* ADS flavours */
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#define CFG_8260ADS 1 /* MPC8260ADS */
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#define CFG_8266ADS 2 /* MPC8266ADS */
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#define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
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#define CFG_8272ADS 4 /* MPC8272ADS */
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#ifndef CONFIG_ADSTYPE
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#define CONFIG_ADSTYPE CFG_8260ADS
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#endif /* CONFIG_ADSTYPE */
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#if CONFIG_ADSTYPE == CFG_8272ADS
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#define CONFIG_MPC8272 1
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#else
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#define CONFIG_MPC8260 1
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#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* allow serial and ethaddr to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#ifdef CONFIG_ETHER_ON_FCC
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#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
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#if CONFIG_ETHER_INDEX == 1
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# define CFG_PHY_ADDR 0
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# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
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# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
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#elif CONFIG_ETHER_INDEX == 2
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#if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
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# define CFG_PHY_ADDR 3
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
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#else /* RxCLK is CLK13, TxCLK is CLK14 */
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# define CFG_PHY_ADDR 0
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
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# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#endif /* CONFIG_ETHER_INDEX */
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#define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 2 /* Port C */
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#if CONFIG_ADSTYPE == CFG_8272ADS
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#define CFG_MDIO_PIN 0x00002000 /* PC18 */
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#define CFG_MDC_PIN 0x00001000 /* PC19 */
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#else
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#define CFG_MDIO_PIN 0x00400000 /* PC9 */
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#define CFG_MDC_PIN 0x00200000 /* PC10 */
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#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
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#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
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#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
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#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
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else iop->pdat &= ~CFG_MDIO_PIN
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#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
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else iop->pdat &= ~CFG_MDC_PIN
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#define MIIDELAY udelay(1)
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#endif /* CONFIG_ETHER_ON_FCC */
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#if CONFIG_ADSTYPE >= CFG_PQ2FADS
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#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
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#else
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
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#define CONFIG_SPD_ADDR 0x50
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#endif
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#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
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/*PCI*/
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#ifdef CONFIG_MPC8272
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_BOOTDELAY 0
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#ifndef CONFIG_SDRAM_PBI
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#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
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#endif
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#ifndef CONFIG_8260_CLKIN
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#if CONFIG_ADSTYPE >= CFG_PQ2FADS
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#define CONFIG_8260_CLKIN 100000000 /* in Hz */
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#else
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#if defined(CONFIG_OF_LIBFDT)
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#define OF_CPU "cpu@0"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_CDP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_PORTIO
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_SDRAM
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#undef CONFIG_CMD_XIMG
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#if CONFIG_ADSTYPE == CFG_8272ADS
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#undef CONFIG_CMD_SDRAM
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#undef CONFIG_CMD_I2C
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#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
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#undef CONFIG_CMD_SDRAM
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#undef CONFIG_CMD_I2C
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#undef CONFIG_CMD_PCI
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#else
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#undef CONFIG_CMD_PCI
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#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
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#if defined(CONFIG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
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#endif
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x400000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_FLASH_BASE 0xff800000
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
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#define CFG_FLASH_SIZE 8
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#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
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#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
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#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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/*
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* JFFS2 partitions
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*
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* Note: fake mtd_id used, no linux mtd map file
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*/
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#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
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#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
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#define CFG_JFFS2_SORT_FRAGMENTS
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/* this is stuff came out of the Motorola docs */
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#ifndef CFG_LOWBOOT
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#define CFG_DEFAULT_IMMR 0x0F010000
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#endif
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#define CFG_IMMR 0xF0000000
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#define CFG_BCSR 0xF4500000
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#if CONFIG_ADSTYPE == CFG_8272ADS
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#define CFG_PCI_INT 0xF8200000
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#endif
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_LSDRAM_BASE 0xFD000000
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#define RS232EN_1 0x02000002
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#define RS232EN_2 0x01000001
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#define FETHIEN1 0x08000008
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#define FETH1_RST 0x04000004
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#define FETHIEN2 0x10000000
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#define FETH2_RST 0x08000000
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#define BCSR_PCI_MODE 0x01000000
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#ifdef CFG_LOWBOOT
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/* PQ2FADS flash HRCW = 0x0EB4B645 */
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#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
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( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
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( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
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( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
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)
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#else
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/* PQ2FADS BCSR HRCW = 0x0CB23645 */
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#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
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( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
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( HRCW_BMS | HRCW_APPC10 ) |\
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( HRCW_MODCK_H0101 ) \
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)
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#endif
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/* no slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#ifdef CONFIG_BZIP2
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#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#else
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
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#endif /* CONFIG_BZIP2 */
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#ifndef CFG_RAMBOOT
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# define CFG_ENV_IS_IN_FLASH 1
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# define CFG_ENV_SECT_SIZE 0x40000
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
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#else
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# define CFG_ENV_IS_IN_NVRAM 1
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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# define CFG_ENV_SIZE 0x200
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#endif /* CFG_RAMBOOT */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
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#define CFG_HID2 0
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#define CFG_SYPCR 0xFFFFFFC3
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#define CFG_BCR 0x100C0000
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#define CFG_SIUMCR 0x0A200000
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#define CFG_SCCR SCCR_DFBRG01
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
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#define CFG_OR0_PRELIM 0xFF800876
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#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801)
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#define CFG_OR1_PRELIM 0xFFFF8010
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/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
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#if CONFIG_ADSTYPE == CFG_8272ADS
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#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */
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#define CFG_OR3_PRELIM 0xFFFF8010
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#endif
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#define CFG_RMR RMR_CSRE
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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#define CFG_RCCR 0
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#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
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#undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */
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#endif /* CONFIG_ADSTYPE == CFG_8266ADS */
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#if CONFIG_ADSTYPE == CFG_PQ2FADS
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#define CFG_OR2 0xFE002EC0
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#define CFG_PSDMR 0x824B36A3
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#define CFG_PSRT 0x13
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#define CFG_LSDMR 0x828737A3
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#define CFG_LSRT 0x13
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#define CFG_MPTPR 0x2800
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#elif CONFIG_ADSTYPE == CFG_8272ADS
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#define CFG_OR2 0xFC002CC0
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#define CFG_PSDMR 0x834E24A3
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#define CFG_PSRT 0x13
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#define CFG_MPTPR 0x2800
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#else
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#define CFG_OR2 0xFF000CA0
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#define CFG_PSDMR 0x016EB452
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#define CFG_PSRT 0x21
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#define CFG_LSDMR 0x0086A522
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#define CFG_LSRT 0x21
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#define CFG_MPTPR 0x1900
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#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
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#define CFG_RESET_ADDRESS 0x04400000
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#if CONFIG_ADSTYPE == CFG_8272ADS
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/* PCI Memory map (if different from default map */
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#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
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#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
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#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
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PICMR_PREFETCH_EN)
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/*
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* These are the windows that allow the CPU to access PCI address space.
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* All three PCI master windows, which allow the CPU to access PCI
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* prefetch, non prefetch, and IO space (see below), must all fit within
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* these windows.
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*/
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/*
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* Master window that allows the CPU to access PCI Memory (prefetch).
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* This window will be setup with the second set of Outbound ATU registers
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* in the bridge.
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*/
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#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
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#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
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#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
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#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
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#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
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/*
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* Master window that allows the CPU to access PCI Memory (non-prefetch).
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* This window will be setup with the second set of Outbound ATU registers
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* in the bridge.
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*/
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#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
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#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
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#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
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#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
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#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
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/*
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* Master window that allows the CPU to access PCI IO space.
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* This window will be setup with the first set of Outbound ATU registers
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* in the bridge.
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*/
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#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
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#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
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#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
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#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
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#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
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/* PCIBR0 - for PCI IO*/
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#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */
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#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
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/* PCIBR1 - prefetch and non-prefetch regions joined together */
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#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL
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#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
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#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
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#if CONFIG_ADSTYPE == CFG_8272ADS
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#define CONFIG_HAS_ETH1
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#endif
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#endif /* __CONFIG_H */
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