705 lines
20 KiB
C
705 lines
20 KiB
C
/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_CPU87 1 /* ...on a CPU87 board */
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#define CONFIG_PCI
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else*/
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
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#define CONFIG_BAUDRATE 230400
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#else
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#define CONFIG_BAUDRATE 9600
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#endif
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_HAS_ETH2 1
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
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/*
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* - Rx-CLK is CLK11
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* - Tx-CLK is CLK12
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
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# define CFG_CPMFCR_RAMTYPE 0
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# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
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#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
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# define CFG_CPMFCR_RAMTYPE 0
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# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
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#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 100000000 /* in Hz */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT \
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"echo; " \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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/*-----------------------------------------------------------------------
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* I2C/EEPROM/RTC configuration
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*/
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#define CONFIG_SOFT_I2C /* Software I2C support enabled */
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# define CFG_I2C_SPEED 50000
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# define CFG_I2C_SLAVE 0xFE
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
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else iop->pdat &= ~0x00010000
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
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else iop->pdat &= ~0x00020000
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CONFIG_RTC_PCF8563
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#define CFG_I2C_RTC_ADDR 0x51
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*-----------------------------------------------------------------------
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* Disk-On-Chip configuration
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*/
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#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
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#define CFG_DOC_SUPPORT_2000
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#define CFG_DOC_SUPPORT_MILLENNIUM
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/*-----------------------------------------------------------------------
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* Miscellaneous configuration options
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DOC
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#endif
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#define CONFIG_NAND_LEGACY
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
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#define CONFIG_LOOPW
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Flash configuration
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*/
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#define CFG_BOOTROM_BASE 0xFF800000
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#define CFG_BOOTROM_SIZE 0x00080000
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#define CFG_FLASH_BASE 0xFF000000
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#define CFG_FLASH_SIZE 0x00800000
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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/*-----------------------------------------------------------------------
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* Other areas to be mapped
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*/
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/* CS3: Dual ported SRAM */
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#define CFG_DPSRAM_BASE 0x40000000
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#define CFG_DPSRAM_SIZE 0x00100000
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/* CS4: DiskOnChip */
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#define CFG_DOC_BASE 0xF4000000
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#define CFG_DOC_SIZE 0x00100000
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/* CS5: FDC37C78 controller */
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#define CFG_FDC37C78_BASE 0xF1000000
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#define CFG_FDC37C78_SIZE 0x00100000
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/* CS6: Board configuration registers */
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#define CFG_BCRS_BASE 0xF2000000
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#define CFG_BCRS_SIZE 0x00010000
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/* CS7: VME Extended Access Range */
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#define CFG_VMEEAR_BASE 0x60000000
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#define CFG_VMEEAR_SIZE 0x01000000
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/* CS8: VME Standard Access Range */
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#define CFG_VMESAR_BASE 0xFE000000
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#define CFG_VMESAR_SIZE 0x01000000
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/* CS9: VME Short I/O Access Range */
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#define CFG_VMESIOAR_BASE 0xFD000000
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#define CFG_VMESIOAR_SIZE 0x01000000
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* if you change bits in the HRCW, you must also change the CFG_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
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*/
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#if defined(CONFIG_BOOT_ROM)
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#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
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HRCW_BPS01 | HRCW_CS10PC01)
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#else
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#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
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#endif
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/* no slaves so just fill with zeros */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*
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* 60x SDRAM is mapped at CFG_SDRAM_BASE.
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT
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#endif
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_EEPRO100
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#endif
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#if 0
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/* environment is in Flash */
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#define CFG_ENV_IS_IN_FLASH 1
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#ifdef CONFIG_BOOT_ROM
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# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
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# define CFG_ENV_SIZE 0x10000
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# define CFG_ENV_SECT_SIZE 0x10000
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#endif
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#else
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/* environment is in EEPROM */
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#define CONFIG_ENV_IS_IN_EEPROM 1
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#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_ENV_OFFSET 512
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#define CFG_ENV_SIZE (2048 - 512)
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
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HID0_DCI|HID0_IFEM|HID0_ABE)
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#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
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#define CFG_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CFG_RMR RMR_CSRE
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define BCR_APD01 0x10000000
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#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
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SIUMCR_CS10PC01|SIUMCR_BCTLC10)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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* Ensure DFBRG is Divide by 16
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*/
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#define CFG_SCCR SCCR_DFBRG01
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0
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#define CFG_MIN_AM_MASK 0xC0000000
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/*
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* we use the same values for 32 MB, 128 MB and 256 MB SDRAM
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* refresh rate = 7.68 uS (100 MHz Bus Clock)
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*/
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/*-----------------------------------------------------------------------
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* MPTPR - Memory Refresh Timer Prescaler Register 10-18
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*-----------------------------------------------------------------------
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*/
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#define CFG_MPTPR 0x2000
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/*-----------------------------------------------------------------------
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* PSRT - Refresh Timer Register 10-16
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*-----------------------------------------------------------------------
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*/
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#define CFG_PSRT 0x16
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/*-----------------------------------------------------------------------
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* PSRT - SDRAM Mode Register 10-10
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*-----------------------------------------------------------------------
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*/
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/* SDRAM initialization values for 8-column chips
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*/
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#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A9 |\
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ORxS_NUMR_12)
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#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
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PSDMR_BSMA_A14_A16 |\
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PSDMR_SDA10_PBI0_A10 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* SDRAM initialization values for 9-column chips
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*/
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#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A7 |\
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ORxS_NUMR_13)
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#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
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PSDMR_BSMA_A13_A15 |\
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PSDMR_SDA10_PBI0_A9 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* SDRAM initialization values for 10-column chips
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*/
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#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI1_A4 |\
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ORxS_NUMR_13)
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#define CFG_PSDMR_10COL (PSDMR_PBI |\
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PSDMR_SDAM_A17_IS_A5 |\
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PSDMR_BSMA_A13_A15 |\
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PSDMR_SDA10_PBI1_A6 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 8 bit Boot ROM
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* 1 60x GPCM 64 bit FLASH
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* 2 60x SDRAM 64 bit SDRAM
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*
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*/
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#define CFG_MRS_OFFS 0x00000000
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#ifdef CONFIG_BOOT_ROM
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/* Bank 0 - Boot ROM
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*/
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#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxU_EHTR_8IDLE)
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/* Bank 1 - FLASH
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*/
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#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxU_EHTR_8IDLE)
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#else /* CONFIG_BOOT_ROM */
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/* Bank 0 - FLASH
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*/
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxU_EHTR_8IDLE)
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/* Bank 1 - Boot ROM
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*/
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#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxU_EHTR_8IDLE)
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#endif /* CONFIG_BOOT_ROM */
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/* Bank 2 - 60x bus SDRAM
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*/
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#ifndef CFG_RAMBOOT
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#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CFG_OR2_PRELIM CFG_OR2_8COL
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#define CFG_PSDMR CFG_PSDMR_8COL
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#endif /* CFG_RAMBOOT */
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/* Bank 3 - Dual Ported SRAM
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*/
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#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_16 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_7_CLK |\
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ORxG_SETA)
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/* Bank 4 - DiskOnChip
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*/
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#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV2 |\
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ORxG_SCY_9_CLK |\
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ORxU_EHTR_8IDLE)
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/* Bank 5 - FDC37C78 controller
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*/
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#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
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ORxG_ACS_DIV2 |\
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ORxG_SCY_10_CLK |\
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ORxU_EHTR_8IDLE)
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/* Bank 6 - Board control registers
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*/
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#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
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ORxG_CSNT |\
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ORxG_SCY_7_CLK)
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/* Bank 7 - VME Extended Access Range
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*/
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#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
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BRx_PS_32 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_7_CLK |\
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ORxG_SETA)
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/* Bank 8 - VME Standard Access Range
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*/
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#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
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BRx_PS_16 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_7_CLK |\
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ORxG_SETA)
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/* Bank 9 - VME Short I/O Access Range
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*/
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#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
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BRx_PS_16 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_7_CLK |\
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ORxG_SETA)
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#endif /* __CONFIG_H */
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