Prabhakar Kushwaha b03a466d6c powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs ... The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-03-29 07:41:37 -05:00
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arm	ARMV7: S5P: Fixed register offset in mmc.h	2011-03-27 19:20:21 +02:00
avr32	rename _end to __bss_end__	2011-03-27 19:18:37 +02:00
blackfin	Introduce a new linker flag LDFLAGS_FINAL	2011-03-22 23:32:06 +01:00
i386	Coding Style cleanup: remove trailing empty lines	2011-03-27 21:48:08 +02:00
m68k	rename _end to __bss_end__	2011-03-27 19:18:37 +02:00
microblaze	microblaze: Fix msr handling in interrupt_handler	2011-02-15 15:13:24 +01:00
mips	Switch from archive libraries to partial linking	2010-11-17 21:02:18 +01:00
nios2	rename _end to __bss_end__	2011-03-27 19:18:37 +02:00
powerpc	powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs	2011-03-29 07:41:37 -05:00
sh	Coding Style cleanup: remove trailing empty lines	2011-03-27 21:48:08 +02:00
sparc	Replace "FLASH" strings with "Flash" or "flash"	2011-01-19 00:02:37 +01:00
.gitignore	update include/asm/ gitignore after move	2010-05-07 00:17:30 +02:00