126 lines
2.9 KiB
C
126 lines
2.9 KiB
C
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_post_init (void)
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{
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return (0);
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}
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int board_init (void)
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{
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/* arch number of IXDP */
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gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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#ifdef CONFIG_IXDPG425
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/* arch number of IXDP */
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gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
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/*
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* Get realtek RTL8305 switch and SLIC out of reset
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*/
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GPIO_OUTPUT_SET(CFG_GPIO_SWITCH_RESET_N);
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GPIO_OUTPUT_ENABLE(CFG_GPIO_SWITCH_RESET_N);
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GPIO_OUTPUT_SET(CFG_GPIO_SLIC_RESET_N);
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GPIO_OUTPUT_ENABLE(CFG_GPIO_SLIC_RESET_N);
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/*
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* Setup GPIO's for PCI INTA & INTB
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*/
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GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA_N);
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GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA_N);
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GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB_N);
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GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB_N);
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/*
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* Setup GPIO's for 33MHz clock output
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*/
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*IXP425_GPIO_GPCLKR = 0x01FF01FF;
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GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK);
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#endif
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return 0;
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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#ifdef CONFIG_IXDPG425
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puts("Board: IXDPG425 - Intel Network Gateway Reference Platform");
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#else
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puts("Board: IXDP425 - Intel Development Platform");
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#endif
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return (0);
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}
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#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
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extern struct pci_controller hose;
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extern void pci_ixp_init(struct pci_controller * hose);
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void pci_init_board(void)
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{
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extern void pci_ixp_init (struct pci_controller *hose);
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pci_ixp_init(&hose);
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}
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#endif
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