b79df8f8f8
add a function in board file to pass board revision info to kernel. Revision number 0 and 1 are passed in case of DM6467 and DM6467T respectively. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
163 lines
5.0 KiB
C
163 lines
5.0 KiB
C
/*
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* Copyright (C) 2009 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Spectrum Digital TMS320DM6467 EVM board */
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#define DAVINCI_DM6467EVM
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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/* Clock rates detection */
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#ifndef __ASSEMBLY__
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extern unsigned int davinci_arm_clk_get(void);
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#endif
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#define CFG_REFCLK_FREQ 27000000
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/* Arm Clock frequency */
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#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
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/* Timer Input clock freq */
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#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SOC_DM646X
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/* EEPROM definitions for EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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/* Memory Info */
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#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
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#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
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/* Linux interfacing */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
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#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
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#define CONFIG_REVISION_TAG
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/* Serial Driver info */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 4
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#define CONFIG_SYS_NS16550_COM1 0x01c20000
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#define CONFIG_SYS_NS16550_CLK 24000000
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* I2C Configuration */
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CONFIG_SYS_I2C_SPEED 80000
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#define CONFIG_SYS_I2C_SLAVE 10
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/* Network & Ethernet Configuration */
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_CMD_NET
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/* Flash & Environment */
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#define CONFIG_SYS_NO_FLASH
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#ifdef CONFIG_SYS_USE_NAND
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NAND_CS 2
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#undef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
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#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
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#define CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_ENV_OFFSET 0
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#else
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
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#endif
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/* U-Boot general configuration */
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
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#define CONFIG_BOOTARGS \
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"mem=120M console=ttyS0,115200n8 " \
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"root=/dev/hda1 rw noinitrd ip=dhcp"
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/* U-Boot commands */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#ifdef CONFIG_SYS_USE_NAND
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_NAND
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#endif
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#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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