b9abcb8c9f
Perform a simple rename of CONFIG_ET1100_BASE to CFG_ET1100_BASE Signed-off-by: Tom Rini <trini@konsulko.com>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2009-2015
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*
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* Configuation settings for the esd MEESC board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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/*
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* Warning: changing CONFIG_TEXT_BASE requires
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* adapting the initial boot program.
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* Since the linker has to swallow that define, we must use a pure
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* hex number here!
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*/
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/* ARM asynchronous clock */
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#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
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#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
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/* Misc CPU related */
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/*
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* Hardware drivers
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*/
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/*
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* SDRAM: 1 bank, min 32, max 128 MB
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* Initialized before u-boot gets started.
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*/
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#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
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#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
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#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
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#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
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#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
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# define CFG_SYS_NAND_MASK_ALE (1 << 21)
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# define CFG_SYS_NAND_MASK_CLE (1 << 22)
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# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
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# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
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#endif
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/* hw-controller addresses */
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#define CFG_ET1100_BASE 0x70000000
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#endif
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