196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Sartura Ltd.
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* Copyright (c) 2022 Linaro Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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* Sumit Garg <sumit.garg@linaro.org>
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*
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* Based on Linux driver
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <reset-uclass.h>
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#include <linux/bitops.h>
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#include <malloc.h>
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struct qcom_reset_priv {
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phys_addr_t base;
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};
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struct qcom_reset_map {
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unsigned int reg;
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u8 bit;
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};
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#ifdef CONFIG_ARCH_IPQ40XX
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#include <dt-bindings/reset/qcom,ipq4019-reset.h>
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static const struct qcom_reset_map gcc_qcom_resets[] = {
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[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
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[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
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[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
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[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
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[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
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[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
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[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
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[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
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[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
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[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
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[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
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[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
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[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
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[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
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[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
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[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
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[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
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[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
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[PCIE_AHB_ARES] = { 0x1d010, 10 },
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[PCIE_PWR_ARES] = { 0x1d010, 9 },
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[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
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[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
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[PCIE_PHY_ARES] = { 0x1d010, 6 },
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[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
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[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
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[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
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[PCIE_PIPE_ARES] = { 0x1d010, 2 },
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[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
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[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
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[ESS_RESET] = { 0x12008, 0},
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[GCC_BLSP1_BCR] = {0x01000, 0},
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[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
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[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
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[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
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[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
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[GCC_BIMC_BCR] = {0x04000, 0},
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[GCC_TLMM_BCR] = {0x05000, 0},
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[GCC_IMEM_BCR] = {0x0E000, 0},
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[GCC_ESS_BCR] = {0x12008, 0},
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[GCC_PRNG_BCR] = {0x13000, 0},
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[GCC_BOOT_ROM_BCR] = {0x13008, 0},
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[GCC_CRYPTO_BCR] = {0x16000, 0},
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[GCC_SDCC1_BCR] = {0x18000, 0},
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[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
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[GCC_AUDIO_BCR] = {0x1B008, 0},
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[GCC_QPIC_BCR] = {0x1C000, 0},
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[GCC_PCIE_BCR] = {0x1D000, 0},
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[GCC_USB2_BCR] = {0x1E008, 0},
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[GCC_USB2_PHY_BCR] = {0x1E018, 0},
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[GCC_USB3_BCR] = {0x1E024, 0},
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[GCC_USB3_PHY_BCR] = {0x1E034, 0},
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[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
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[GCC_PCNOC_BCR] = {0x2102C, 0},
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[GCC_DCD_BCR] = {0x21038, 0},
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[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
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[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
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[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
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[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
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[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
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[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
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[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
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[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
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[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
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[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
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[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
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[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
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[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
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[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
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[GCC_TCSR_BCR] = {0x22000, 0},
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[GCC_MPM_BCR] = {0x24000, 0},
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[GCC_SPDM_BCR] = {0x25000, 0},
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};
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#endif
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#ifdef CONFIG_TARGET_QCS404EVB
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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static const struct qcom_reset_map gcc_qcom_resets[] = {
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[GCC_GENI_IR_BCR] = { 0x0F000 },
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[GCC_CDSP_RESTART] = { 0x18000 },
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[GCC_USB_HS_BCR] = { 0x41000 },
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[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
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[GCC_QUSB2_PHY_BCR] = { 0x4103c },
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[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
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[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
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[GCC_USB3_PHY_BCR] = { 0x39004 },
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[GCC_USB_30_BCR] = { 0x39000 },
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[GCC_USB3PHY_PHY_BCR] = { 0x39008 },
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[GCC_PCIE_0_BCR] = { 0x3e000 },
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[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
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[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
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[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
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[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
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[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
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[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
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[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
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[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
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[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
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[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
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[GCC_EMAC_BCR] = { 0x4e000 },
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[GCC_WDSP_RESTART] = {0x19000},
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};
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#endif
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static int qcom_reset_assert(struct reset_ctl *rst)
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{
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struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
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const struct qcom_reset_map *reset_map = gcc_qcom_resets;
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const struct qcom_reset_map *map;
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u32 value;
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map = &reset_map[rst->id];
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value = readl(priv->base + map->reg);
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value |= BIT(map->bit);
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writel(value, priv->base + map->reg);
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return 0;
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}
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static int qcom_reset_deassert(struct reset_ctl *rst)
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{
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struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
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const struct qcom_reset_map *reset_map = gcc_qcom_resets;
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const struct qcom_reset_map *map;
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u32 value;
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map = &reset_map[rst->id];
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value = readl(priv->base + map->reg);
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value &= ~BIT(map->bit);
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writel(value, priv->base + map->reg);
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return 0;
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}
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static const struct reset_ops qcom_reset_ops = {
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.rst_assert = qcom_reset_assert,
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.rst_deassert = qcom_reset_deassert,
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};
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static const struct udevice_id qcom_reset_ids[] = {
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{ .compatible = "qcom,gcc-reset-ipq4019" },
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{ .compatible = "qcom,gcc-reset-qcs404" },
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{ }
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};
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static int qcom_reset_probe(struct udevice *dev)
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{
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struct qcom_reset_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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U_BOOT_DRIVER(qcom_reset) = {
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.name = "qcom_reset",
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.id = UCLASS_RESET,
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.of_match = qcom_reset_ids,
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.ops = &qcom_reset_ops,
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.probe = qcom_reset_probe,
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.priv_auto = sizeof(struct qcom_reset_priv),
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};
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