2ed96a87d2
This has been done in order to align the DT of U-Boot with the DT of Linux. In Linux, a phandle from a '-gpio' DT property is linked to the pinctrl driver, a single driver that handles both pinctrl settings and offers GPIO API to callers. On the other hand, U-Boot redirects such phandle to a corresponding UCLASS_GPIO driver, because U-Boot offers two different types of drivers in this case: UCLASS_PINCTRL which handles pin functions and UCLASS_GPIO which handles gpio requests as a gpio provider. Due to this, we have two drivers in Uboot, but the Devicetree has a single node. Thus, just one of the drivers can be probed for the DT node during platform initialization, before relocation. Our previous solution in U-Boot was to have a different devicetree: the gpio node has a subnode for the pinctrl driver, which is not compliant with Linux ABI. Furthermore, our documentation for this type of nodes mentions no such gpio compatible. After this patch, we can no longer add nodes with a gpio compatible in the DT. Thus, in order to link the pinctrl driver to the gpio one, a hook to the bind method of the former in U-Boot has been added and the GPIO related compatibles have been removed to avoid conflict when compatibles are enumerated and bound to drivers during platform start before relocation. The bind method will attach the GPIO driver to the pinctrl DT node so that every phandle coming from '-gpio' DT properties will be redirected to a valid driver attached to the pinctrl DT node. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
371 lines
8.3 KiB
C
371 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Atmel PIO4 device driver
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*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/arch/hardware.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <linux/bitops.h>
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#include <mach/gpio.h>
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#include <mach/atmel_pio4.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
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{
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struct atmel_pio4_port *base = NULL;
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switch (port) {
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case AT91_PIO_PORTA:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
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break;
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case AT91_PIO_PORTB:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
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break;
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case AT91_PIO_PORTC:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
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break;
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case AT91_PIO_PORTD:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
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break;
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#if (ATMEL_PIO_PORTS > 4)
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case AT91_PIO_PORTE:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOE;
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break;
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#endif
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default:
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printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
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port);
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break;
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}
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return base;
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}
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static int atmel_pio4_config_io_func(u32 port, u32 pin,
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u32 func, u32 config)
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{
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struct atmel_pio4_port *port_base;
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u32 reg, mask;
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if (pin >= ATMEL_PIO_NPINS_PER_BANK)
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return -EINVAL;
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port_base = atmel_pio4_port_base(port);
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if (!port_base)
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return -EINVAL;
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mask = 1 << pin;
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reg = func;
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reg |= config;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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return 0;
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}
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int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_GPIO,
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config);
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}
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int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_A,
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config);
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}
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int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_B,
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config);
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}
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int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_C,
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config);
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}
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int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_D,
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config);
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}
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int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_E,
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config);
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}
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int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_F,
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config);
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}
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int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO_CFGR_FUNC_PERIPH_G,
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config);
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}
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int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
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{
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struct atmel_pio4_port *port_base;
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u32 reg, mask;
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if (pin >= ATMEL_PIO_NPINS_PER_BANK)
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return -EINVAL;
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port_base = atmel_pio4_port_base(port);
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if (!port_base)
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return -EINVAL;
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mask = 0x01 << pin;
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reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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if (value)
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writel(mask, &port_base->sodr);
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else
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writel(mask, &port_base->codr);
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return 0;
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}
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int atmel_pio4_get_pio_input(u32 port, u32 pin)
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{
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struct atmel_pio4_port *port_base;
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u32 reg, mask;
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if (pin >= ATMEL_PIO_NPINS_PER_BANK)
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return -EINVAL;
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port_base = atmel_pio4_port_base(port);
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if (!port_base)
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return -EINVAL;
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mask = 0x01 << pin;
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reg = ATMEL_PIO_CFGR_FUNC_GPIO;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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return (readl(&port_base->pdsr) & mask) ? 1 : 0;
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}
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#if CONFIG_IS_ENABLED(DM_GPIO)
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/**
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* struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
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* @nbanks: number of PIO banks
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* @last_bank_count: number of lines in the last bank (can be less than
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* the rest of the banks).
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*/
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struct atmel_pioctrl_data {
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u32 nbanks;
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u32 last_bank_count;
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};
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struct atmel_pio4_plat {
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struct atmel_pio4_port *reg_base;
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};
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static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
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u32 bank)
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{
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struct atmel_pio4_plat *plat = dev_get_plat(dev);
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struct atmel_pio4_port *port_base =
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(struct atmel_pio4_port *)((u32)plat->reg_base +
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ATMEL_PIO_BANK_OFFSET * bank);
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return port_base;
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}
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static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
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{
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u32 bank = ATMEL_PIO_BANK(offset);
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u32 line = ATMEL_PIO_LINE(offset);
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struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
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u32 mask = BIT(line);
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writel(mask, &port_base->mskr);
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clrbits_le32(&port_base->cfgr,
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ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
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return 0;
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}
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static int atmel_pio4_direction_output(struct udevice *dev,
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unsigned offset, int value)
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{
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u32 bank = ATMEL_PIO_BANK(offset);
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u32 line = ATMEL_PIO_LINE(offset);
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struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
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u32 mask = BIT(line);
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writel(mask, &port_base->mskr);
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clrsetbits_le32(&port_base->cfgr,
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ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
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if (value)
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writel(mask, &port_base->sodr);
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else
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writel(mask, &port_base->codr);
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return 0;
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}
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static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
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{
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u32 bank = ATMEL_PIO_BANK(offset);
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u32 line = ATMEL_PIO_LINE(offset);
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struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
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u32 mask = BIT(line);
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return (readl(&port_base->pdsr) & mask) ? 1 : 0;
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}
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static int atmel_pio4_set_value(struct udevice *dev,
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unsigned offset, int value)
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{
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u32 bank = ATMEL_PIO_BANK(offset);
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u32 line = ATMEL_PIO_LINE(offset);
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struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
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u32 mask = BIT(line);
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if (value)
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writel(mask, &port_base->sodr);
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else
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writel(mask, &port_base->codr);
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return 0;
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}
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static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
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{
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u32 bank = ATMEL_PIO_BANK(offset);
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u32 line = ATMEL_PIO_LINE(offset);
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struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
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u32 mask = BIT(line);
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writel(mask, &port_base->mskr);
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return (readl(&port_base->cfgr) &
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ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static const struct dm_gpio_ops atmel_pio4_ops = {
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.direction_input = atmel_pio4_direction_input,
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.direction_output = atmel_pio4_direction_output,
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.get_value = atmel_pio4_get_value,
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.set_value = atmel_pio4_set_value,
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.get_function = atmel_pio4_get_function,
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};
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static int atmel_pio4_bind(struct udevice *dev)
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{
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return dm_scan_fdt_dev(dev);
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}
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static int atmel_pio4_probe(struct udevice *dev)
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{
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struct atmel_pio4_plat *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct atmel_pioctrl_data *pioctrl_data;
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struct clk clk;
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fdt_addr_t addr_base;
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u32 nbanks;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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clk_free(&clk);
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addr_base = dev_read_addr(dev);
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if (addr_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->reg_base = (struct atmel_pio4_port *)addr_base;
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pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
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nbanks = pioctrl_data->nbanks;
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uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
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NULL);
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uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
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/* if last bank has limited number of pins, adjust accordingly */
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if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
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uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
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uc_priv->gpio_count += pioctrl_data->last_bank_count;
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}
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return 0;
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}
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/*
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* The number of banks can be different from a SoC to another one.
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* We can have up to 16 banks.
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*/
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static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
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.nbanks = 4,
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.last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
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};
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static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
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.nbanks = 5,
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.last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
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};
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static const struct udevice_id atmel_pio4_ids[] = {
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{
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.data = (ulong)&atmel_sama5d2_pioctrl_data,
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}, {
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.data = (ulong)µchip_sama7g5_pioctrl_data,
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},
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{}
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};
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U_BOOT_DRIVER(gpio_atmel_pio4) = {
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.name = "gpio_atmel_pio4",
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.id = UCLASS_GPIO,
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.ops = &atmel_pio4_ops,
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.probe = atmel_pio4_probe,
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.bind = atmel_pio4_bind,
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.of_match = atmel_pio4_ids,
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.plat_auto = sizeof(struct atmel_pio4_plat),
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};
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#endif
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