3e12f7f036
Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
33 lines
1.3 KiB
ReStructuredText
33 lines
1.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
|
|
|
|
ARC
|
|
===
|
|
|
|
Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
|
|
that SoC designers can optimize for a wide range of uses, from deeply embedded
|
|
to high-performance host applications.
|
|
|
|
More information on ARC cores avaialble here:
|
|
http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
|
|
|
|
Designers can differentiate their products by using patented configuration
|
|
technology to tailor each ARC processor instance to meet specific performance,
|
|
power and area requirements.
|
|
|
|
The DesignWare ARC processors are also extendable, allowing designers to add
|
|
their own custom instructions that dramatically increase performance.
|
|
|
|
Synopsys' ARC processors have been used by over 170 customers worldwide who
|
|
collectively ship more than 1 billion ARC-based chips annually.
|
|
|
|
All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
|
|
performance and code density for embedded and host SoC applications.
|
|
|
|
The RISC microprocessors are synthesizable and can be implemented in any foundry
|
|
or process, and are supported by a complete suite of development tools.
|
|
|
|
The ARC GNU toolchain with support for all ARC Processors can be downloaded
|
|
from here (available pre-built toolchains as well):
|
|
|
|
https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
|