864ac2cf38
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
153 lines
3.5 KiB
C
153 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Amarula Solutions(India)
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* Authors:
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* Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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* Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/ddr.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#if CONFIG_IS_ENABLED(POWER_LEGACY)
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#define I2C_PMIC 0
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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ret = power_pca9450_init(I2C_PMIC, 0x25);
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if (ret)
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printf("power init failed");
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p = pmic_get("PCA9450");
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pmic_probe(p);
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
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#ifdef CONFIG_IMX8M_LPDDR4
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/*
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* increase VDD_SOC to typical value 0.95V before first
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* DRAM access, set DVS1 to 0.85v for suspend.
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
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*/
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#ifdef CONFIG_IMX8M_VDD_SOC_850MV
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/* set DVS0 to 0.85v for special case*/
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
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#else
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
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#endif
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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/* Kernel uses OD/OD freq for SOC */
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/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
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pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
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#elif defined(CONFIG_IMX8M_DDR4)
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/* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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/* Set NVCC_DRAM to 1.2v for DDR4 */
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pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
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#endif
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/* set WDOG_B_CFG to cold reset */
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pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
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return 0;
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}
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#endif
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void spl_board_init(void)
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{
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/* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it.
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* Should set the clock after PMIC setting done.
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* Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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}
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