60df809f62
This commit adds support for the B&R brsmarc1 SoM. The SoM is based on TI's AM335x SoC. Mainly vxWorks 6.9.4.x is running on the board, doing some PLC stuff on various carrier boards. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
267 lines
9.5 KiB
C
267 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* mux.c
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*
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* Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
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*
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* Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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static struct module_pin_mux spi0_pin_mux[] = {
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/* SPI0_SCLK */
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{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI0_D0 */
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{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI0_D1 */
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{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI0_CS0 */
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{OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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/* SPI0_CS1 */
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{OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux spi1_pin_mux[] = {
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/* SPI1_SCLK */
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{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
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/* SPI1_D0 */
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{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
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/* SPI1_D1 */
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{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
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/* SPI1_CS0 */
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{OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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/* SPI1_CS1 */
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{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux dcan0_pin_mux[] = {
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/* DCAN0 TX */
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{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
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/* DCAN0 RX */
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{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux dcan1_pin_mux[] = {
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/* DCAN1 TX */
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{OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
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/* DCAN1 RX */
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{OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux gpios[] = {
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/* GPIO0_7 - LVDS_EN */
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO0_20 - BKLT_PWM (timer7) */
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{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO2_4 - DISON */
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{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO1_24 - RGB_EN */
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{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO1_28 - nPD */
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{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
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/* GPIO2_5 - Watchdog */
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{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO2_0 - ResetOut */
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{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
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/* GPIO2_2 - BKLT_EN */
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{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO1_17 - GPIO0 */
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{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_18 - GPIO1 */
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{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_19 - GPIO2 */
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{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_22 - GPIO3 */
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{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_23 - GPIO4 */
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{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_25 - GPIO5 */
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{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_7 - GPIO6 */
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{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_8 - GPIO7 */
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{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_18 - GPIO8 */
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{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_19 - GPIO9 */
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{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_20 - GPIO10 */
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{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_21 - GPIO11 */
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{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO2_28 - DRAM-strapping */
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{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
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/* GPIO2_4 - not routed (Pin U6) */
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{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO2_5 - not routed (Pin T6) */
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{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO2_28 - not routed (Pin G15) */
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{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO3_18 - not routed (Pin B12) */
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{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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{-1},
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};
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static struct module_pin_mux uart0_pin_mux[] = {
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/* UART0_RXD */
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_TXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux uart234_pin_mux[] = {
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/* UART2_RXD */
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{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART2_TXD */
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{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
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/* UART3_RXD */
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{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART3_TXD */
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{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
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/* UART3_RTS */
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{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
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/* UART3_CTS */
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{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART4_RXD */
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{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART4_TXD */
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{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
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/* UART4_RTS */
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{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
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/* UART4_CTS */
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{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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{-1},
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};
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static struct module_pin_mux i2c_pin_mux[] = {
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/* I2C0_DATA */
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C0_SCLK */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C1_DATA */
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{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C1_SCLK */
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{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux eth_pin_mux[] = {
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/* ETH1 */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
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{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
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{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
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{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
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{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
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{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
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{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
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/* ETH2 */
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{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
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{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
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{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
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{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
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{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
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{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
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{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
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{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
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/* gpio2_19, gpio 3_4, not connected on board */
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{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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/* ETH Management */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
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{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
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{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
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{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{-1},
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};
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static struct module_pin_mux lcd_pin_mux[] = {
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{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
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{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
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{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
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{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
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{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
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{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
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{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
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{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
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{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
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{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
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{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
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{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
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{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
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{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
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{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
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{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
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{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
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{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
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{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
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{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
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{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
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{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
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{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
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{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
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{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
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{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
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{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
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{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
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{-1},
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};
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_i2c_pin_mux(void)
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{
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configure_module_pin_mux(i2c_pin_mux);
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}
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void enable_board_pin_mux(void)
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{
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configure_module_pin_mux(eth_pin_mux);
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configure_module_pin_mux(spi0_pin_mux);
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configure_module_pin_mux(spi1_pin_mux);
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configure_module_pin_mux(dcan0_pin_mux);
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configure_module_pin_mux(dcan1_pin_mux);
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configure_module_pin_mux(uart234_pin_mux);
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configure_module_pin_mux(mmc1_pin_mux);
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configure_module_pin_mux(lcd_pin_mux);
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configure_module_pin_mux(gpios);
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}
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