Prepare v2022.07-rc6

Signed-off-by: Tom Rini <trini@konsulko.com>

MAINTAINERS

@@ -121,6 +121,7 @@ F:	arch/arm/include/asm/arch-m1/
 F:	arch/arm/mach-apple/
 F:	configs/apple_m1_defconfig
 F:	drivers/iommu/apple_dart.c
+F:	drivers/nvme/nvme_apple.c
 F:	drivers/pinctrl/pinctrl-apple.c
 F:	drivers/watchdog/apple_wdt.c
 F:	include/configs/apple.h
@@ -1063,8 +1064,9 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
 F:	drivers/mmc/
 
 NAND FLASH
-#M:	Scott Wood <oss@buserror.net>
-S:	Orphaned (Since 2018-07)
+M:	Dario Binacchi <dario.binacchi@amarulasolutions.com>
+M:	Michael Trimarchi <michael@amarulasolutions.com>
+S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
 F:	drivers/mtd/nand/raw/
 

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2022
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME =
 
 # *DOCUMENTATION*

arch/arm/cpu/armv7/sunxi/psci.c

@@ -153,7 +153,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
 
 	sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
 			   (void *)cpucfg + SUN8I_R40_PWROFF,
-			   on, 0);
+			   on, cpu);
 }
 #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
 static void __secure sunxi_cpu_set_power(int cpu, bool on)

arch/arm/dts/Makefile

@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_agilex_socdk.dtb			\
 	socfpga_arria5_secu1.dtb			\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_arria10_chameleonv3_270_3.dtb		\
+	socfpga_arria10_chameleonv3_480_2.dtb		\
 	socfpga_arria10_socdk_sdmmc.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_is1.dtb			\
@@ -539,7 +541,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-olinuxino-lime.dtb \
 	sun4i-a10-pcduino.dtb \
 	sun4i-a10-pcduino2.dtb \
-	sun4i-a10-pov-protab2-ips9.dtb
+	sun4i-a10-pov-protab2-ips9.dtb \
+	sun4i-a10-topwise-a721.dtb
 dtb-$(CONFIG_MACH_SUN5I) += \
 	sun5i-a10s-auxtek-t003.dtb \
 	sun5i-a10s-auxtek-t004.dtb \

arch/arm/dts/axp209.dtsi

@@ -53,7 +53,7 @@
 	interrupt-controller;
 	#interrupt-cells = <1>;
 
-	ac_power_supply: ac-power-supply {
+	ac_power_supply: ac-power {
 		compatible = "x-powers,axp202-ac-power-supply";
 		status = "disabled";
 	};
@@ -69,7 +69,7 @@
 		#gpio-cells = <2>;
 	};
 
-	battery_power_supply: battery-power-supply {
+	battery_power_supply: battery-power {
 		compatible = "x-powers,axp209-battery-power-supply";
 		status = "disabled";
 	};
@@ -112,7 +112,7 @@
 		};
 	};
 
-	usb_power_supply: usb-power-supply {
+	usb_power_supply: usb-power {
 		compatible = "x-powers,axp202-usb-power-supply";
 		status = "disabled";
 	};

arch/arm/dts/imx8mm-kontron-n801x-s.dts

@@ -6,7 +6,6 @@
 /dts-v1/;
 
 #include "imx8mm-kontron-n801x-som.dtsi"
-#include <dt-bindings/net/mscc-phy-vsc8531.h>
 
 / {
 	model = "Kontron i.MX8MM N801X S";
@@ -81,7 +80,6 @@
 		regulator-name = "vdd-5v";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
 	};
 };
 
@@ -124,38 +122,14 @@
 		#size-cells = <0>;
 
 		ethphy: ethernet-phy@0 {
-			compatible = "ethernet-phy-id0007.0570";
 			reg = <0>;
-			reset-assert-us = <100>;
-			reset-deassert-us = <100>;
+			reset-assert-us = <1>;
+			reset-deassert-us = <15000>;
 			reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
-			vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
-			vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
-			vsc8531,led-0-combine-disable;
 		};
 	};
 };
 
-&gpio4 {
-	dsi_mux_sel: dsi_mux_sel {
-		gpio-hog;
-		gpios = <14 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "dsi-mux-sel";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_dsi_sel>;
-	};
-
-	dsi_mux_oe {
-		gpio-hog;
-		gpios = <15 GPIO_ACTIVE_LOW>;
-		output-high;
-		line-name = "dsi-mux-oe";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_dsi_oe>;
-	};
-};
-
 &i2c4 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
@@ -208,7 +182,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		usbnet: usbether@1 {
+		usbnet: ethernet@1 {
 			compatible = "usb424,ec00";
 			reg = <1>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
@@ -237,18 +211,6 @@
 		>;
 	};
 
-	pinctrl_dsi_sel: dsiselgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19
-		>;
-	};
-
-	pinctrl_dsi_oe: dsioegrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19
-		>;
-	};
-
 	pinctrl_ecspi2: ecspi2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
@@ -362,7 +324,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
@@ -374,7 +336,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6

arch/arm/dts/imx8mm-kontron-n801x-som.dtsi

@@ -63,10 +63,10 @@
 &ecspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
-	spi-flash@0 {
+	flash@0 {
 		compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
 		spi-max-frequency = <80000000>;
 		reg = <0>;
@@ -154,7 +154,7 @@
 			reg_vdd_snvs: LDO2 {
 				regulator-name = "ldo2";
 				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
+				regulator-max-microvolt = <900000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};

arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi

@@ -25,10 +25,23 @@
 	};
 };
 
-&fec1 {
-	phy-mode = "rgmii-rxid";
+&crypto {
+	u-boot,dm-spl;
 };
 
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+
 &i2c1 {
 	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;

arch/arm/dts/rk3188.dtsi

@@ -642,8 +642,7 @@
 	compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
 
 	usbphy: usbphy {
-		compatible = "rockchip,rk3188-usb-phy",
-			     "rockchip,rk3288-usb-phy";
+		compatible = "rockchip,rk3188-usb-phy";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

arch/arm/dts/rk3288-evb.dtsi

@@ -448,7 +448,7 @@
 	status = "okay";
 };
 
-&mipi_dsi0 {
+&mipi_dsi {
 	status = "disabled";
 	rockchip,panel = <&panel>;
 	display-timings {

arch/arm/dts/rk3288.dtsi

@@ -86,47 +86,6 @@
 		};
 	};
 
-	amba {
-		compatible = "arm,amba-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		dmac_peri: dma-controller@ff250000 {
-			compatible = "arm,pl330", "arm,primecell";
-			broken-no-flushp;
-			reg = <0xff250000 0x4000>;
-			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			clocks = <&cru ACLK_DMAC2>;
-			clock-names = "apb_pclk";
-		};
-
-		dmac_bus_ns: dma-controller@ff600000 {
-			compatible = "arm,pl330", "arm,primecell";
-			broken-no-flushp;
-			reg = <0xff600000 0x4000>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			clocks = <&cru ACLK_DMAC1>;
-			clock-names = "apb_pclk";
-			status = "disabled";
-		};
-
-		dmac_bus_s: dma-controller@ffb20000 {
-			compatible = "arm,pl330", "arm,primecell";
-			broken-no-flushp;
-			reg = <0xffb20000 0x4000>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			clocks = <&cru ACLK_DMAC1>;
-			clock-names = "apb_pclk";
-		};
-	};
-
 	xin24m: oscillator {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
@@ -367,6 +326,18 @@
 		pinctrl-0 = <&uart4_xfer>;
 		status = "disabled";
 	};
+
+	dmac_peri: dma-controller@ff250000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0xff250000 0x4000>;
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		broken-no-flushp;
+		clocks = <&cru ACLK_DMAC2>;
+		clock-names = "apb_pclk";
+	};
+
 	thermal: thermal-zones {
 		#include "rk3288-thermal.dtsi"
 	};
@@ -458,6 +429,18 @@
 		status = "disabled";
 	};
 
+	dmac_bus_ns: dma-controller@ff600000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0xff600000 0x4000>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		broken-no-flushp;
+		clocks = <&cru ACLK_DMAC1>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
 	i2c0: i2c@ff650000 {
 		compatible = "rockchip,rk3288-i2c";
 		reg = <0xff650000 0x1000>;
@@ -709,7 +692,63 @@
 		status = "disabled";
 	};
 
-	edp: edp@ff970000 {
+	mipi_dsi: mipi@ff960000 {
+		compatible = "rockchip,rk3288_mipi_dsi";
+		reg = <0xff960000 0x4000>;
+		clocks = <&cru PCLK_MIPI_DSI0>;
+		clock-names = "pclk_mipi";
+		/*pinctrl-names = "default";
+		pinctrl-0 = <&lcdc0_ctl>;*/
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		ports {
+			reg = <1>;
+			mipi_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mipi_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_mipi>;
+				};
+				mipi_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_mipi>;
+				};
+			};
+		};
+	};
+
+	lvds: lvds@ff96c000 {
+		compatible = "rockchip,rk3288-lvds";
+		reg = <0xff96c000 0x4000>;
+		clocks = <&cru PCLK_LVDS_PHY>;
+		clock-names = "pclk_lvds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcdc0_ctl>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			lvds_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				lvds_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_lvds>;
+				};
+				lvds_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_lvds>;
+				};
+			};
+		};
+	};
+
+	edp: dp@ff970000 {
 		compatible = "rockchip,rk3288-edp";
 		reg = <0xff970000 0x4000>;
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -762,62 +801,6 @@
 		};
 	};
 
-	lvds: lvds@ff96c000 {
-		compatible = "rockchip,rk3288-lvds";
-		reg = <0xff96c000 0x4000>;
-		clocks = <&cru PCLK_LVDS_PHY>;
-		clock-names = "pclk_lvds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&lcdc0_ctl>;
-		rockchip,grf = <&grf>;
-		status = "disabled";
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			lvds_in: port@0 {
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				lvds_in_vopb: endpoint@0 {
-					reg = <0>;
-					remote-endpoint = <&vopb_out_lvds>;
-				};
-				lvds_in_vopl: endpoint@1 {
-					reg = <1>;
-					remote-endpoint = <&vopl_out_lvds>;
-				};
-			};
-		};
-	};
-
-	mipi_dsi0: mipi@ff960000 {
-		compatible = "rockchip,rk3288_mipi_dsi";
-		reg = <0xff960000 0x4000>;
-		clocks = <&cru PCLK_MIPI_DSI0>;
-		clock-names = "pclk_mipi";
-		/*pinctrl-names = "default";
-		pinctrl-0 = <&lcdc0_ctl>;*/
-		rockchip,grf = <&grf>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-		ports {
-			reg = <1>;
-			mipi_in: port {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				mipi_in_vopb: endpoint@0 {
-					reg = <0>;
-					remote-endpoint = <&vopb_out_mipi>;
-				};
-				mipi_in_vopl: endpoint@1 {
-					reg = <1>;
-					remote-endpoint = <&vopl_out_mipi>;
-				};
-			};
-		};
-	};
-
 	hdmi_audio: hdmi_audio {
 		compatible = "rockchip,rk3288-hdmi-audio";
 		i2s-controller = <&i2s>;
@@ -870,6 +853,17 @@
 		status = "disabled";
 	};
 
+	dmac_bus_s: dma-controller@ffb20000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0xffb20000 0x4000>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		broken-no-flushp;
+		clocks = <&cru ACLK_DMAC1>;
+		clock-names = "apb_pclk";
+	};
+
 	efuse: efuse@ffb40000 {
 		compatible = "rockchip,rk3288-efuse";
 		reg = <0xffb40000 0x10000>;
@@ -1072,411 +1066,411 @@
 
 		sleep {
 			global_pwroff: global-pwroff {
-				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
 			};
 
 			ddrio_pwroff: ddrio-pwroff {
-				rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
 			};
 
 			ddr0_retention: ddr0-retention {
-				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
 			};
 
 			ddr1_retention: ddr1-retention {
-				rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
 			};
 		};
 
 		i2c0 {
 			i2c0_xfer: i2c0-xfer {
-				rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
-						<0 16 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
+						<0 RK_PC0 1 &pcfg_pull_none>;
 			};
 		};
 
 		i2c1 {
 			i2c1_xfer: i2c1-xfer {
-				rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
-						<8 5 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
+						<8 RK_PA5 1 &pcfg_pull_none>;
 			};
 		};
 
 		i2c2 {
 			i2c2_xfer: i2c2-xfer {
-				rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
-						<6 10 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
+						<6 RK_PB2 1 &pcfg_pull_none>;
 			};
 		};
 
 		i2c3 {
 			i2c3_xfer: i2c3-xfer {
-				rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
-						<2 17 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
+						<2 RK_PC1 1 &pcfg_pull_none>;
 			};
 		};
 
 		i2c4 {
 			i2c4_xfer: i2c4-xfer {
-				rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
-						<7 18 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
+						<7 RK_PC2 1 &pcfg_pull_none>;
 			};
 		};
 
 		i2c5 {
 			i2c5_xfer: i2c5-xfer {
-				rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
-						<7 20 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
+						<7 RK_PC4 1 &pcfg_pull_none>;
 			};
 		};
 
 		i2s0 {
 			i2s0_bus: i2s0-bus {
-				rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
-						<6 1 RK_FUNC_1 &pcfg_pull_none>,
-						<6 2 RK_FUNC_1 &pcfg_pull_none>,
-						<6 3 RK_FUNC_1 &pcfg_pull_none>,
-						<6 4 RK_FUNC_1 &pcfg_pull_none>,
-						<6 8 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
+						<6 RK_PA1 1 &pcfg_pull_none>,
+						<6 RK_PA2 1 &pcfg_pull_none>,
+						<6 RK_PA3 1 &pcfg_pull_none>,
+						<6 RK_PA4 1 &pcfg_pull_none>,
+						<6 RK_PB0 1 &pcfg_pull_none>;
 			};
 		};
 
 		lcdc0 {
 			lcdc0_ctl: lcdc0-ctl {
-				rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
-						<1 25 RK_FUNC_1 &pcfg_pull_none>,
-						<1 26 RK_FUNC_1 &pcfg_pull_none>,
-						<1 27 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
+						<1 RK_PD1 1 &pcfg_pull_none>,
+						<1 RK_PD2 1 &pcfg_pull_none>,
+						<1 RK_PD3 1 &pcfg_pull_none>;
 			};
 		};
 
 		sdmmc {
 			sdmmc_clk: sdmmc-clk {
-				rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
 			};
 
 			sdmmc_cmd: sdmmc-cmd {
-				rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
 			};
 
 			sdmmc_cd: sdmcc-cd {
-				rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
 			};
 
 			sdmmc_bus1: sdmmc-bus1 {
-				rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
 			};
 
 			sdmmc_bus4: sdmmc-bus4 {
-				rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
-						<6 17 RK_FUNC_1 &pcfg_pull_up>,
-						<6 18 RK_FUNC_1 &pcfg_pull_up>,
-						<6 19 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
+						<6 RK_PC1 1 &pcfg_pull_up>,
+						<6 RK_PC2 1 &pcfg_pull_up>,
+						<6 RK_PC3 1 &pcfg_pull_up>;
 			};
 		};
 
 		sdio0 {
 			sdio0_bus1: sdio0-bus1 {
-				rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
 			};
 
 			sdio0_bus4: sdio0-bus4 {
-				rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
-						<4 21 RK_FUNC_1 &pcfg_pull_up>,
-						<4 22 RK_FUNC_1 &pcfg_pull_up>,
-						<4 23 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
+						<4 RK_PC5 1 &pcfg_pull_up>,
+						<4 RK_PC6 1 &pcfg_pull_up>,
+						<4 RK_PC7 1 &pcfg_pull_up>;
 			};
 
 			sdio0_cmd: sdio0-cmd {
-				rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
 			};
 
 			sdio0_clk: sdio0-clk {
-				rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
 			};
 
 			sdio0_cd: sdio0-cd {
-				rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
 			};
 
 			sdio0_wp: sdio0-wp {
-				rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
 			};
 
 			sdio0_pwr: sdio0-pwr {
-				rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
 			};
 
 			sdio0_bkpwr: sdio0-bkpwr {
-				rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
 			};
 
 			sdio0_int: sdio0-int {
-				rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
 			};
 		};
 
 		sdio1 {
 			sdio1_bus1: sdio1-bus1 {
-				rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
 			};
 
 			sdio1_bus4: sdio1-bus4 {
-				rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
-						<3 25 RK_FUNC_4 &pcfg_pull_up>,
-						<3 26 RK_FUNC_4 &pcfg_pull_up>,
-						<3 27 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
+						<3 RK_PD1 4 &pcfg_pull_up>,
+						<3 RK_PD2 4 &pcfg_pull_up>,
+						<3 RK_PD3 4 &pcfg_pull_up>;
 			};
 
 			sdio1_cd: sdio1-cd {
-				rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
 			};
 
 			sdio1_wp: sdio1-wp {
-				rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
 			};
 
 			sdio1_bkpwr: sdio1-bkpwr {
-				rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
 			};
 
 			sdio1_int: sdio1-int {
-				rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
 			};
 
 			sdio1_cmd: sdio1-cmd {
-				rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
 			};
 
 			sdio1_clk: sdio1-clk {
-				rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+				rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
 			};
 
 			sdio1_pwr: sdio1-pwr {
-				rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+				rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
 			};
 		};
 
 		emmc {
 			emmc_clk: emmc-clk {
-				rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+				rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
 			};
 
 			emmc_cmd: emmc-cmd {
-				rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
 			};
 
 			emmc_pwr: emmc-pwr {
-				rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
 			};
 
 			emmc_bus1: emmc-bus1 {
-				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
 			};
 
 			emmc_bus4: emmc-bus4 {
-				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
-						<3 1 RK_FUNC_2 &pcfg_pull_up>,
-						<3 2 RK_FUNC_2 &pcfg_pull_up>,
-						<3 3 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
+						<3 RK_PA1 2 &pcfg_pull_up>,
+						<3 RK_PA2 2 &pcfg_pull_up>,
+						<3 RK_PA3 2 &pcfg_pull_up>;
 			};
 
 			emmc_bus8: emmc-bus8 {
-				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
-						<3 1 RK_FUNC_2 &pcfg_pull_up>,
-						<3 2 RK_FUNC_2 &pcfg_pull_up>,
-						<3 3 RK_FUNC_2 &pcfg_pull_up>,
-						<3 4 RK_FUNC_2 &pcfg_pull_up>,
-						<3 5 RK_FUNC_2 &pcfg_pull_up>,
-						<3 6 RK_FUNC_2 &pcfg_pull_up>,
-						<3 7 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
+						<3 RK_PA1 2 &pcfg_pull_up>,
+						<3 RK_PA2 2 &pcfg_pull_up>,
+						<3 RK_PA3 2 &pcfg_pull_up>,
+						<3 RK_PA4 2 &pcfg_pull_up>,
+						<3 RK_PA5 2 &pcfg_pull_up>,
+						<3 RK_PA6 2 &pcfg_pull_up>,
+						<3 RK_PA7 2 &pcfg_pull_up>;
 			};
 		};
 
 		spi0 {
 			spi0_clk: spi0-clk {
-				rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
 			};
 			spi0_cs0: spi0-cs0 {
-				rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
 			};
 			spi0_tx: spi0-tx {
-				rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
 			};
 			spi0_rx: spi0-rx {
-				rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
 			};
 			spi0_cs1: spi0-cs1 {
-				rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
 			};
 		};
 		spi1 {
 			spi1_clk: spi1-clk {
-				rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
 			};
 			spi1_cs0: spi1-cs0 {
-				rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
 			};
 			spi1_rx: spi1-rx {
-				rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
 			};
 			spi1_tx: spi1-tx {
-				rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
+				rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
 			};
 		};
 
 		spi2 {
 			spi2_cs1: spi2-cs1 {
-				rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
 			};
 			spi2_clk: spi2-clk {
-				rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
 			};
 			spi2_cs0: spi2-cs0 {
-				rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
 			};
 			spi2_rx: spi2-rx {
-				rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
 			};
 			spi2_tx: spi2-tx {
-				rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
+				rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
 			};
 		};
 
 		uart0 {
 			uart0_xfer: uart0-xfer {
-				rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
-						<4 17 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
+						<4 RK_PC1 1 &pcfg_pull_none>;
 			};
 
 			uart0_cts: uart0-cts {
-				rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>;
 			};
 
 			uart0_rts: uart0-rts {
-				rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
 			};
 		};
 
 		uart1 {
 			uart1_xfer: uart1-xfer {
-				rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
-						<5 9 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
+						<5 RK_PB1 1 &pcfg_pull_none>;
 			};
 
 			uart1_cts: uart1-cts {
-				rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>;
 			};
 
 			uart1_rts: uart1-rts {
-				rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
 			};
 		};
 
 		uart2 {
 			uart2_xfer: uart2-xfer {
-				rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
-						<7 23 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
+						<7 RK_PC7 1 &pcfg_pull_none>;
 			};
 			/* no rts / cts for uart2 */
 		};
 
 		uart3 {
 			uart3_xfer: uart3-xfer {
-				rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
-						<7 8 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
+						<7 RK_PB0 1 &pcfg_pull_none>;
 			};
 
 			uart3_cts: uart3-cts {
-				rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>;
 			};
 
 			uart3_rts: uart3-rts {
-				rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
 			};
 		};
 
 		uart4 {
 			uart4_xfer: uart4-xfer {
-				rockchip,pins = <5 12 3 &pcfg_pull_up>,
-						<5 13 3 &pcfg_pull_none>;
+				rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>,
+						<5 RK_PB5 3 &pcfg_pull_none>;
 			};
 
 			uart4_cts: uart4-cts {
-				rockchip,pins = <5 14 3 &pcfg_pull_none>;
+				rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>;
 			};
 
 			uart4_rts: uart4-rts {
-				rockchip,pins = <5 15 3 &pcfg_pull_none>;
+				rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>;
 			};
 		};
 
 		tsadc {
 			otp_out: otp-out {
-				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
 			};
 		};
 
 		pwm0 {
 			pwm0_pin: pwm0-pin {
-				rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
 			};
 		};
 
 		pwm1 {
 			pwm1_pin: pwm1-pin {
-				rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
 			};
 		};
 
 		pwm2 {
 			pwm2_pin: pwm2-pin {
-				rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
 			};
 		};
 
 		pwm3 {
 			pwm3_pin: pwm3-pin {
-				rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
+				rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
 			};
 		};
 
 		gmac {
 			rgmii_pins: rgmii-pins {
-				rockchip,pins = <3 30 3 &pcfg_pull_none>,
-						<3 31 3 &pcfg_pull_none>,
-						<3 26 3 &pcfg_pull_none>,
-						<3 27 3 &pcfg_pull_none>,
-						<3 28 3 &pcfg_pull_none_12ma>,
-						<3 29 3 &pcfg_pull_none_12ma>,
-						<3 24 3 &pcfg_pull_none_12ma>,
-						<3 25 3 &pcfg_pull_none_12ma>,
-						<4 0 3 &pcfg_pull_none>,
-						<4 5 3 &pcfg_pull_none>,
-						<4 6 3 &pcfg_pull_none>,
-						<4 9 3 &pcfg_pull_none_12ma>,
-						<4 4 3 &pcfg_pull_none_12ma>,
-						<4 1 3 &pcfg_pull_none>,
-						<4 3 3 &pcfg_pull_none>;
+				rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
+						<3 RK_PD7 3 &pcfg_pull_none>,
+						<3 RK_PD2 3 &pcfg_pull_none>,
+						<3 RK_PD3 3 &pcfg_pull_none>,
+						<3 RK_PD4 3 &pcfg_pull_none_12ma>,
+						<3 RK_PD5 3 &pcfg_pull_none_12ma>,
+						<3 RK_PD0 3 &pcfg_pull_none_12ma>,
+						<3 RK_PD1 3 &pcfg_pull_none_12ma>,
+						<4 RK_PA0 3 &pcfg_pull_none>,
+						<4 RK_PA5 3 &pcfg_pull_none>,
+						<4 RK_PA6 3 &pcfg_pull_none>,
+						<4 RK_PB1 3 &pcfg_pull_none_12ma>,
+						<4 RK_PA4 3 &pcfg_pull_none_12ma>,
+						<4 RK_PA1 3 &pcfg_pull_none>,
+						<4 RK_PA3 3 &pcfg_pull_none>;
 			};
 
 			rmii_pins: rmii-pins {
-				rockchip,pins = <3 30 3 &pcfg_pull_none>,
-						<3 31 3 &pcfg_pull_none>,
-						<3 28 3 &pcfg_pull_none>,
-						<3 29 3 &pcfg_pull_none>,
-						<4 0 3 &pcfg_pull_none>,
-						<4 5 3 &pcfg_pull_none>,
-						<4 4 3 &pcfg_pull_none>,
-						<4 1 3 &pcfg_pull_none>,
-						<4 2 3 &pcfg_pull_none>,
-						<4 3 3 &pcfg_pull_none>;
+				rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
+						<3 RK_PD7 3 &pcfg_pull_none>,
+						<3 RK_PD4 3 &pcfg_pull_none>,
+						<3 RK_PD5 3 &pcfg_pull_none>,
+						<4 RK_PA0 3 &pcfg_pull_none>,
+						<4 RK_PA5 3 &pcfg_pull_none>,
+						<4 RK_PA4 3 &pcfg_pull_none>,
+						<4 RK_PA1 3 &pcfg_pull_none>,
+						<4 RK_PA2 3 &pcfg_pull_none>,
+						<4 RK_PA3 3 &pcfg_pull_none>;
 			};
 		};
 
 		spdif {
 			spdif_tx: spdif-tx {
-				rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
 			};
 		};
 	};

arch/arm/dts/rk3399-pinebook-pro.dts

@@ -17,6 +17,7 @@
 / {
 	model = "Pine64 Pinebook Pro";
 	compatible = "pine64,pinebook-pro", "rockchip,rk3399";
+	chassis-type = "laptop";
 
 	aliases {
 		mmc0 = &sdio0;
@@ -242,12 +243,12 @@
 	vdd_log: vdd-log {
 		compatible = "pwm-regulator";
 		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc_sysin>;
 		regulator-name = "vdd_log";
 		regulator-always-on;
 		regulator-boot-on;
 		regulator-min-microvolt = <800000>;
 		regulator-max-microvolt = <1400000>;
-		vin-supply = <&vcc_sysin>;
 
 		regulator-state-mem {
 			regulator-on-in-suspend;
@@ -385,10 +386,6 @@
 	};
 };
 
-&cdn_dp {
-	status = "okay";
-};
-
 &cpu_b0 {
 	cpu-supply = <&vdd_cpu_b>;
 };
@@ -475,8 +472,6 @@
 		vcc10-supply = <&vcc_sysin>;
 		vcc11-supply = <&vcc_sysin>;
 		vcc12-supply = <&vcc3v3_sys>;
-		vcc13-supply = <&vcc_sysin>;
-		vcc14-supply = <&vcc_sysin>;
 
 		regulators {
 			/* rk3399 center logic supply */
@@ -711,7 +706,7 @@
 
 		connector {
 			compatible = "usb-c-connector";
-			data-role = "host";
+			data-role = "dual";
 			label = "USB-C";
 			op-sink-microwatt = <1000000>;
 			power-role = "dual";

arch/arm/dts/socfpga_arria10_chameleonv3.dts

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+	model = "Google Chameleon V3";
+	compatible = "google,chameleon-v3",
+		     "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		serial0 = &uart0;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	ssm2603: ssm2603@1a {
+		compatible = "adi,ssm2603";
+		reg = <0x1a>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	u80: u80@21 {
+		compatible = "nxp,pca9535";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names =
+			"SOM_AUD_MUTE",
+			"DP1_OUT_CEC_EN",
+			"DP2_OUT_CEC_EN",
+			"DP1_SOM_PS8469_CAD",
+			"DPD_SOM_PS8469_CAD",
+			"DP_OUT_PWR_EN",
+			"STM32_RST_L",
+			"STM32_BOOT0",
+
+			"FPGA_PROT",
+			"STM32_FPGA_COMM0",
+			"TP119",
+			"TP120",
+			"TP121",
+			"TP122",
+			"TP123",
+			"TP124";
+	};
+};
+
+&mmc {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};

arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"

arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dts"

arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h

@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 33330000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 200000000
+#define H2F_USER1_CLK_HZ 100000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 15
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1584
+#define PERPLLGRP_CNTR2CLK_CNT 5
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 14
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 374
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1485
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 7
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+	(ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+	(ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 0
+#define CONFIG_IO_12_PD_DRV_STRG 0
+#define CONFIG_IO_12_PD_SLW_RT 0
+#define CONFIG_IO_12_PU_DRV_STRG 0
+#define CONFIG_IO_12_PU_SLW_RT 0
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 0
+#define CONFIG_IO_13_PD_DRV_STRG 0
+#define CONFIG_IO_13_PD_SLW_RT 0
+#define CONFIG_IO_13_PU_DRV_STRG 0
+#define CONFIG_IO_13_PU_SLW_RT 0
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 0
+#define CONFIG_IO_14_PD_DRV_STRG 0
+#define CONFIG_IO_14_PD_SLW_RT 0
+#define CONFIG_IO_14_PU_DRV_STRG 0
+#define CONFIG_IO_14_PU_SLW_RT 0
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 0
+#define CONFIG_IO_15_PD_DRV_STRG 0
+#define CONFIG_IO_15_PD_SLW_RT 0
+#define CONFIG_IO_15_PU_DRV_STRG 0
+#define CONFIG_IO_15_PU_SLW_RT 0
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STRG 8
+#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_RTRIM 1
+#define CONFIG_IO_16_WK_PU_EN 0
+#define CONFIG_IO_17_INPUT_BUF_EN 1
+#define CONFIG_IO_17_PD_DRV_STRG 10
+#define CONFIG_IO_17_PD_SLW_RT 1
+#define CONFIG_IO_17_PU_DRV_STRG 8
+#define CONFIG_IO_17_PU_SLW_RT 1
+#define CONFIG_IO_17_RTRIM 1
+#define CONFIG_IO_17_WK_PU_EN 0
+#define CONFIG_IO_1_INPUT_BUF_EN 1
+#define CONFIG_IO_1_PD_DRV_STRG 10
+#define CONFIG_IO_1_PD_SLW_RT 0
+#define CONFIG_IO_1_PU_DRV_STRG 8
+#define CONFIG_IO_1_PU_SLW_RT 0
+#define CONFIG_IO_1_RTRIM 1
+#define CONFIG_IO_1_WK_PU_EN 1
+#define CONFIG_IO_2_INPUT_BUF_EN 1
+#define CONFIG_IO_2_PD_DRV_STRG 10
+#define CONFIG_IO_2_PD_SLW_RT 0
+#define CONFIG_IO_2_PU_DRV_STRG 8
+#define CONFIG_IO_2_PU_SLW_RT 0
+#define CONFIG_IO_2_RTRIM 1
+#define CONFIG_IO_2_WK_PU_EN 1
+#define CONFIG_IO_3_INPUT_BUF_EN 1
+#define CONFIG_IO_3_PD_DRV_STRG 10
+#define CONFIG_IO_3_PD_SLW_RT 0
+#define CONFIG_IO_3_PU_DRV_STRG 8
+#define CONFIG_IO_3_PU_SLW_RT 0
+#define CONFIG_IO_3_RTRIM 1
+#define CONFIG_IO_3_WK_PU_EN 1
+#define CONFIG_IO_4_INPUT_BUF_EN 1
+#define CONFIG_IO_4_PD_DRV_STRG 10
+#define CONFIG_IO_4_PD_SLW_RT 1
+#define CONFIG_IO_4_PU_DRV_STRG 8
+#define CONFIG_IO_4_PU_SLW_RT 1
+#define CONFIG_IO_4_RTRIM 1
+#define CONFIG_IO_4_WK_PU_EN 0
+#define CONFIG_IO_5_INPUT_BUF_EN 1
+#define CONFIG_IO_5_PD_DRV_STRG 10
+#define CONFIG_IO_5_PD_SLW_RT 1
+#define CONFIG_IO_5_PU_DRV_STRG 8
+#define CONFIG_IO_5_PU_SLW_RT 1
+#define CONFIG_IO_5_RTRIM 1
+#define CONFIG_IO_5_WK_PU_EN 0
+#define CONFIG_IO_6_INPUT_BUF_EN 0
+#define CONFIG_IO_6_PD_DRV_STRG 10
+#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PU_DRV_STRG 8
+#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_RTRIM 1
+#define CONFIG_IO_6_WK_PU_EN 0
+#define CONFIG_IO_7_INPUT_BUF_EN 1
+#define CONFIG_IO_7_PD_DRV_STRG 10
+#define CONFIG_IO_7_PD_SLW_RT 1
+#define CONFIG_IO_7_PU_DRV_STRG 8
+#define CONFIG_IO_7_PU_SLW_RT 1
+#define CONFIG_IO_7_RTRIM 1
+#define CONFIG_IO_7_WK_PU_EN 0
+#define CONFIG_IO_8_INPUT_BUF_EN 1
+#define CONFIG_IO_8_PD_DRV_STRG 10
+#define CONFIG_IO_8_PD_SLW_RT 1
+#define CONFIG_IO_8_PU_DRV_STRG 8
+#define CONFIG_IO_8_PU_SLW_RT 1
+#define CONFIG_IO_8_RTRIM 1
+#define CONFIG_IO_8_WK_PU_EN 0
+#define CONFIG_IO_9_INPUT_BUF_EN 1
+#define CONFIG_IO_9_PD_DRV_STRG 10
+#define CONFIG_IO_9_PD_SLW_RT 1
+#define CONFIG_IO_9_PU_DRV_STRG 8
+#define CONFIG_IO_9_PU_SLW_RT 1
+#define CONFIG_IO_9_RTRIM 1
+#define CONFIG_IO_9_WK_PU_EN 0
+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 15
+#define PINMUX_DEDICATED_IO_11_SEL 15
+#define PINMUX_DEDICATED_IO_12_SEL 1
+#define PINMUX_DEDICATED_IO_13_SEL 1
+#define PINMUX_DEDICATED_IO_14_SEL 10
+#define PINMUX_DEDICATED_IO_15_SEL 10
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 8
+#define PINMUX_DEDICATED_IO_5_SEL 8
+#define PINMUX_DEDICATED_IO_6_SEL 8
+#define PINMUX_DEDICATED_IO_7_SEL 8
+#define PINMUX_DEDICATED_IO_8_SEL 8
+#define PINMUX_DEDICATED_IO_9_SEL 8
+#define PINMUX_I2C0_USEFPGA_SEL 1
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 15
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 15
+#define PINMUX_SHARED_IO_Q3_2_SEL 15
+#define PINMUX_SHARED_IO_Q3_3_SEL 15
+#define PINMUX_SHARED_IO_Q3_4_SEL 15
+#define PINMUX_SHARED_IO_Q3_5_SEL 15
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 0
+#define PINMUX_SHARED_IO_Q3_8_SEL 0
+#define PINMUX_SHARED_IO_Q3_9_SEL 15
+#define PINMUX_SHARED_IO_Q4_10_SEL 10
+#define PINMUX_SHARED_IO_Q4_11_SEL 10
+#define PINMUX_SHARED_IO_Q4_12_SEL 10
+#define PINMUX_SHARED_IO_Q4_1_SEL 10
+#define PINMUX_SHARED_IO_Q4_2_SEL 10
+#define PINMUX_SHARED_IO_Q4_3_SEL 10
+#define PINMUX_SHARED_IO_Q4_4_SEL 10
+#define PINMUX_SHARED_IO_Q4_5_SEL 10
+#define PINMUX_SHARED_IO_Q4_6_SEL 10
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 10
+#define PINMUX_SHARED_IO_Q4_9_SEL 10
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 1
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 1
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for Config IO */
+#define CONFIG_IO_BANK_VSEL \
+	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for Config IO bit mapping */
+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+	((NAME ## _WK_PU_EN & 0x1) << 16) | \
+	((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+	((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+	(NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"

arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dts"

arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h

@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 33330000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 200000000
+#define H2F_USER1_CLK_HZ 100000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 9
+#define MAINPLLGRP_CNTR7CLK_CNT 9
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 19
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1980
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1980
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 9
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+	(ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+	(ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 0
+#define CONFIG_IO_12_PD_DRV_STRG 0
+#define CONFIG_IO_12_PD_SLW_RT 0
+#define CONFIG_IO_12_PU_DRV_STRG 0
+#define CONFIG_IO_12_PU_SLW_RT 0
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 0
+#define CONFIG_IO_13_PD_DRV_STRG 0
+#define CONFIG_IO_13_PD_SLW_RT 0
+#define CONFIG_IO_13_PU_DRV_STRG 0
+#define CONFIG_IO_13_PU_SLW_RT 0
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 0
+#define CONFIG_IO_14_PD_DRV_STRG 0
+#define CONFIG_IO_14_PD_SLW_RT 0
+#define CONFIG_IO_14_PU_DRV_STRG 0
+#define CONFIG_IO_14_PU_SLW_RT 0
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 0
+#define CONFIG_IO_15_PD_DRV_STRG 0
+#define CONFIG_IO_15_PD_SLW_RT 0
+#define CONFIG_IO_15_PU_DRV_STRG 0
+#define CONFIG_IO_15_PU_SLW_RT 0
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STRG 8
+#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_RTRIM 1
+#define CONFIG_IO_16_WK_PU_EN 0
+#define CONFIG_IO_17_INPUT_BUF_EN 1
+#define CONFIG_IO_17_PD_DRV_STRG 10
+#define CONFIG_IO_17_PD_SLW_RT 1
+#define CONFIG_IO_17_PU_DRV_STRG 8
+#define CONFIG_IO_17_PU_SLW_RT 1
+#define CONFIG_IO_17_RTRIM 1
+#define CONFIG_IO_17_WK_PU_EN 0
+#define CONFIG_IO_1_INPUT_BUF_EN 1
+#define CONFIG_IO_1_PD_DRV_STRG 10
+#define CONFIG_IO_1_PD_SLW_RT 0
+#define CONFIG_IO_1_PU_DRV_STRG 8
+#define CONFIG_IO_1_PU_SLW_RT 0
+#define CONFIG_IO_1_RTRIM 1
+#define CONFIG_IO_1_WK_PU_EN 1
+#define CONFIG_IO_2_INPUT_BUF_EN 1
+#define CONFIG_IO_2_PD_DRV_STRG 10
+#define CONFIG_IO_2_PD_SLW_RT 0
+#define CONFIG_IO_2_PU_DRV_STRG 8
+#define CONFIG_IO_2_PU_SLW_RT 0
+#define CONFIG_IO_2_RTRIM 1
+#define CONFIG_IO_2_WK_PU_EN 1
+#define CONFIG_IO_3_INPUT_BUF_EN 1
+#define CONFIG_IO_3_PD_DRV_STRG 10
+#define CONFIG_IO_3_PD_SLW_RT 0
+#define CONFIG_IO_3_PU_DRV_STRG 8
+#define CONFIG_IO_3_PU_SLW_RT 0
+#define CONFIG_IO_3_RTRIM 1
+#define CONFIG_IO_3_WK_PU_EN 1
+#define CONFIG_IO_4_INPUT_BUF_EN 1
+#define CONFIG_IO_4_PD_DRV_STRG 10
+#define CONFIG_IO_4_PD_SLW_RT 1
+#define CONFIG_IO_4_PU_DRV_STRG 8
+#define CONFIG_IO_4_PU_SLW_RT 1
+#define CONFIG_IO_4_RTRIM 1
+#define CONFIG_IO_4_WK_PU_EN 0
+#define CONFIG_IO_5_INPUT_BUF_EN 1
+#define CONFIG_IO_5_PD_DRV_STRG 10
+#define CONFIG_IO_5_PD_SLW_RT 1
+#define CONFIG_IO_5_PU_DRV_STRG 8
+#define CONFIG_IO_5_PU_SLW_RT 1
+#define CONFIG_IO_5_RTRIM 1
+#define CONFIG_IO_5_WK_PU_EN 0
+#define CONFIG_IO_6_INPUT_BUF_EN 0
+#define CONFIG_IO_6_PD_DRV_STRG 10
+#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PU_DRV_STRG 8
+#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_RTRIM 1
+#define CONFIG_IO_6_WK_PU_EN 0
+#define CONFIG_IO_7_INPUT_BUF_EN 1
+#define CONFIG_IO_7_PD_DRV_STRG 10
+#define CONFIG_IO_7_PD_SLW_RT 1
+#define CONFIG_IO_7_PU_DRV_STRG 8
+#define CONFIG_IO_7_PU_SLW_RT 1
+#define CONFIG_IO_7_RTRIM 1
+#define CONFIG_IO_7_WK_PU_EN 0
+#define CONFIG_IO_8_INPUT_BUF_EN 1
+#define CONFIG_IO_8_PD_DRV_STRG 10
+#define CONFIG_IO_8_PD_SLW_RT 1
+#define CONFIG_IO_8_PU_DRV_STRG 8
+#define CONFIG_IO_8_PU_SLW_RT 1
+#define CONFIG_IO_8_RTRIM 1
+#define CONFIG_IO_8_WK_PU_EN 0
+#define CONFIG_IO_9_INPUT_BUF_EN 1
+#define CONFIG_IO_9_PD_DRV_STRG 10
+#define CONFIG_IO_9_PD_SLW_RT 1
+#define CONFIG_IO_9_PU_DRV_STRG 8
+#define CONFIG_IO_9_PU_SLW_RT 1
+#define CONFIG_IO_9_RTRIM 1
+#define CONFIG_IO_9_WK_PU_EN 0
+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 15
+#define PINMUX_DEDICATED_IO_11_SEL 15
+#define PINMUX_DEDICATED_IO_12_SEL 1
+#define PINMUX_DEDICATED_IO_13_SEL 1
+#define PINMUX_DEDICATED_IO_14_SEL 10
+#define PINMUX_DEDICATED_IO_15_SEL 10
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 8
+#define PINMUX_DEDICATED_IO_5_SEL 8
+#define PINMUX_DEDICATED_IO_6_SEL 8
+#define PINMUX_DEDICATED_IO_7_SEL 8
+#define PINMUX_DEDICATED_IO_8_SEL 8
+#define PINMUX_DEDICATED_IO_9_SEL 8
+#define PINMUX_I2C0_USEFPGA_SEL 1
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 15
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 15
+#define PINMUX_SHARED_IO_Q3_2_SEL 15
+#define PINMUX_SHARED_IO_Q3_3_SEL 15
+#define PINMUX_SHARED_IO_Q3_4_SEL 15
+#define PINMUX_SHARED_IO_Q3_5_SEL 15
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 0
+#define PINMUX_SHARED_IO_Q3_8_SEL 0
+#define PINMUX_SHARED_IO_Q3_9_SEL 15
+#define PINMUX_SHARED_IO_Q4_10_SEL 10
+#define PINMUX_SHARED_IO_Q4_11_SEL 10
+#define PINMUX_SHARED_IO_Q4_12_SEL 10
+#define PINMUX_SHARED_IO_Q4_1_SEL 10
+#define PINMUX_SHARED_IO_Q4_2_SEL 10
+#define PINMUX_SHARED_IO_Q4_3_SEL 10
+#define PINMUX_SHARED_IO_Q4_4_SEL 10
+#define PINMUX_SHARED_IO_Q4_5_SEL 10
+#define PINMUX_SHARED_IO_Q4_6_SEL 10
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 10
+#define PINMUX_SHARED_IO_Q4_9_SEL 10
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 1
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 1
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for Config IO */
+#define CONFIG_IO_BANK_VSEL \
+	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for Config IO bit mapping */
+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+	((NAME ## _WK_PU_EN & 0x1) << 16) | \
+	((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+	((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+	(NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi

@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+	chosen {
+		firmware-loader = <&fs_loader0>;
+	};
+
+	fs_loader0: fs-loader {
+		u-boot,dm-pre-reloc;
+		compatible = "u-boot,fs-loader";
+		phandlepart = <&mmc 1>;
+	};
+};
+
+&atsha204a {
+	u-boot,dm-pre-reloc;
+};
+
+&fpga_mgr {
+	u-boot,dm-pre-reloc;
+	altr,bitstream = "fpga.itb";
+};
+
+&i2c1 {
+	u-boot,dm-pre-reloc;
+};
+
+&main_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi

@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+	aliases {
+		ethernet0 = &gmac0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	phy-handle = <&phy3>;
+
+	max-frame-size = <3800>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy3: ethernet-phy@3 {
+			reg = <3>;
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <1860>; /* 960ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
+&i2c1 {
+	atsha204a: atsha204a@64 {
+		compatible = "atmel,atsha204a";
+		reg = <0x64>;
+	};
+
+	isl12022: isl12022@6f {
+		compatible = "isil,isl12022";
+		reg = <0x6f>;
+	};
+};
+
+&mmc {
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+};
+
+&osc1 {
+	clock-frequency = <33330000>;
+};

arch/arm/dts/sun4i-a10-a1000.dts

@@ -60,15 +60,26 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
-		red {
+		led-0 {
 			label = "a1000:red:usr";
 			gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
 		};
 
-		blue {
+		led-1 {
 			label = "a1000:blue:pwr";
 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
@@ -125,7 +136,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -133,6 +144,20 @@
 	status = "okay";
 };
 
+&de {
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 

arch/arm/dts/sun4i-a10-ba10-tvbox.dts

@@ -68,7 +68,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts

@@ -131,20 +131,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &reg_usb0_vbus {
 	status = "okay";
 };
@@ -165,10 +151,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-cubieboard.dts

@@ -75,12 +75,12 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&led_pins_cubieboard>;
 
-		blue {
+		led-0 {
 			label = "cubieboard:blue:usr";
 			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
 		};
 
-		green {
+		led-1 {
 			label = "cubieboard:green:usr";
 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
 			linux,default-trigger = "heartbeat";
@@ -114,7 +114,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -184,12 +184,6 @@
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
-
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
 };
 
 &reg_ahci_5v {
@@ -254,9 +248,7 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts

@@ -62,6 +62,7 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_vcc3v3>;
 	};
 
 	chosen {
@@ -158,20 +159,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pwm0_pin>;
@@ -223,10 +210,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-hackberry.dts

@@ -80,7 +80,7 @@
 };
 
 &emac {
-	phy = <&phy0>;
+	phy-handle = <&phy0>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-hyundai-a7hd.dts

@@ -86,20 +86,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &reg_usb0_vbus {
 	status = "okay";
 };
@@ -121,10 +107,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-inet1.dts

@@ -62,6 +62,7 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_vcc3v3>;
 	};
 
 	chosen {
@@ -164,20 +165,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pwm0_pin>;
@@ -233,10 +220,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;

arch/arm/dts/sun4i-a10-inet9f-rev03.dts

@@ -61,10 +61,6 @@
 
 	gpio-keys {
 		compatible = "gpio-keys-polled";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key_pins_inet9f>;
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <20>;
 
 		left-joystick-left {
@@ -72,7 +68,7 @@
 			linux,code = <ABS_X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
+			gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
 		};
 
 		left-joystick-right {
@@ -80,7 +76,7 @@
 			linux,code = <ABS_X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
+			gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
 		};
 
 		left-joystick-up {
@@ -88,7 +84,7 @@
 			linux,code = <ABS_Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
+			gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
 		};
 
 		left-joystick-down {
@@ -96,7 +92,7 @@
 			linux,code = <ABS_Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+			gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
 		};
 
 		right-joystick-left {
@@ -104,7 +100,7 @@
 			linux,code = <ABS_Z>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
+			gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
 		};
 
 		right-joystick-right {
@@ -112,7 +108,7 @@
 			linux,code = <ABS_Z>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
+			gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
 		};
 
 		right-joystick-up {
@@ -120,7 +116,7 @@
 			linux,code = <ABS_RZ>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
+			gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
 		};
 
 		right-joystick-down {
@@ -128,7 +124,7 @@
 			linux,code = <ABS_RZ>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
+			gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
 		};
 
 		dpad-left {
@@ -136,7 +132,7 @@
 			linux,code = <ABS_HAT0X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
+			gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
 		};
 
 		dpad-right {
@@ -144,7 +140,7 @@
 			linux,code = <ABS_HAT0X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+			gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
 		};
 
 		dpad-up {
@@ -152,7 +148,7 @@
 			linux,code = <ABS_HAT0Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+			gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
 		};
 
 		dpad-down {
@@ -160,55 +156,55 @@
 			linux,code = <ABS_HAT0Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+			gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
 		};
 
 		x {
 			label = "Button X";
 			linux,code = <BTN_X>;
-			gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
+			gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
 		};
 
 		y {
 			label = "Button Y";
 			linux,code = <BTN_Y>;
-			gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
+			gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
 		};
 
 		a {
 			label = "Button A";
 			linux,code = <BTN_A>;
-			gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+			gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
 		};
 
 		b {
 			label = "Button B";
 			linux,code = <BTN_B>;
-			gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
+			gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
 		};
 
 		select {
 			label = "Select Button";
 			linux,code = <BTN_SELECT>;
-			gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
+			gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
 		};
 
 		start {
 			label = "Start Button";
 			linux,code = <BTN_START>;
-			gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
+			gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
 		};
 
 		top-left {
 			label = "Top Left Button";
 			linux,code = <BTN_TL>;
-			gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
+			gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
 		};
 
 		top-right {
 			label = "Top Right Button";
 			linux,code = <BTN_TR>;
-			gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
+			gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
 		};
 	};
 };
@@ -308,30 +304,6 @@
 	status = "okay";
 };
 
-&pio {
-	key_pins_inet9f: key-pins {
-		pins = "PA0", "PA1", "PA3", "PA4",
-		       "PA5", "PA6", "PA8", "PA9",
-		       "PA11", "PA12", "PA13",
-		       "PA14", "PA15", "PA16", "PA17",
-		       "PH22", "PH23", "PH24", "PH25", "PH26";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &reg_dcdc2 {
 	regulator-always-on;
 	regulator-min-microvolt = <1000000>;
@@ -377,10 +349,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts

@@ -58,7 +58,7 @@
 &emac {
 	pinctrl-names = "default";
 	pinctrl-0 = <&emac_pins>;
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-jesurun-q5.dts

@@ -63,7 +63,7 @@
 	leds {
 		compatible = "gpio-leds";
 
-		green {
+		led {
 			label = "q5:green:usr";
 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;  /* PH20 */
 		};
@@ -94,7 +94,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-marsboard.dts

@@ -62,22 +62,22 @@
 	leds {
 		compatible = "gpio-leds";
 
-		red1 {
+		led-0 {
 			label = "marsboard:red1:usr";
 			gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
 		};
 
-		red2 {
+		led-1 {
 			label = "marsboard:red2:usr";
 			gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
 		};
 
-		red3 {
+		led-2 {
 			label = "marsboard:red3:usr";
 			gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
 		};
 
-		red4 {
+		led-3 {
 			label = "marsboard:red4:usr";
 			gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
 		};
@@ -105,7 +105,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -148,14 +148,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-};
-
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -183,9 +175,7 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-olinuxino-lime.dts

@@ -74,7 +74,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&led_pins_olinuxinolime>;
 
-		green {
+		led {
 			label = "a10-olinuxino-lime:green:usr";
 			gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
@@ -91,12 +91,11 @@
 	/*
 	 * The A10-Lime is known to be unstable when running at 1008 MHz
 	 */
-	operating-points = <
+	operating-points =
 		/* kHz	  uV */
-		912000  1350000
-		864000  1300000
-		624000  1250000
-		>;
+		<912000	1350000>,
+		<864000	1300000>,
+		<624000	1250000>;
 };
 
 &de {
@@ -112,7 +111,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -186,18 +185,6 @@
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
-
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
 };
 
 &reg_ahci_5v {
@@ -229,10 +216,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio   = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */
 	usb0_vbus-supply   = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;

arch/arm/dts/sun4i-a10-pcduino.dts

@@ -63,12 +63,12 @@
 	leds {
 		compatible = "gpio-leds";
 
-		tx {
+		led-0 {
 			label = "pcduino:green:tx";
 			gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
 		};
 
-		rx {
+		led-1 {
 			label = "pcduino:green:rx";
 			gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
 		};
@@ -76,8 +76,6 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
 		back {
 			label = "Key Back";
@@ -112,7 +110,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -156,14 +154,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-};
-
 #include "axp209.dtsi"
 
 &reg_dcdc2 {
@@ -203,9 +193,7 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
 	usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
 	usb2_vbus-supply = <&reg_vcc5v0>; /* USB2 VBUS is always on */
 	status = "okay";

arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts

@@ -62,6 +62,7 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_vcc3v3>;
 	};
 
 	chosen {
@@ -146,20 +147,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pwm0_pin>;
@@ -211,10 +198,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-topwise-a721.dts

@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Pascal Roeleven <dev@pascalroeleven.nl>
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Topwise A721";
+	compatible = "topwise,a721", "allwinner,sun4i-a10";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_vbat>;
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		brightness-levels = <0 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	panel {
+		compatible = "starry,kr070pe2t";
+		backlight = <&backlight>;
+		power-supply = <&reg_lcd_power>;
+
+		port {
+			panel_input: endpoint {
+				remote-endpoint = <&tcon0_out_panel>;
+			};
+		};
+	};
+
+	reg_lcd_power: reg-lcd-power {
+		compatible = "regulator-fixed";
+		regulator-name = "reg-lcd-power";
+		gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+		enable-active-high;
+	};
+
+	reg_vbat: reg-vbat {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+	};
+
+};
+
+&codec {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&de {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+		interrupts = <0>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+	status = "okay";
+};
+
+&battery_power_supply {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	accelerometer@4c {
+		compatible = "fsl,mma7660";
+		reg = <0x4c>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		vcc-supply = <&reg_vcc3v3>;
+	};
+};
+
+&lradc {
+	vref-supply = <&reg_ldo2>;
+	status = "okay";
+
+	button-571 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <571428>;
+	};
+
+	button-761 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <761904>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	vcc-pb-supply = <&reg_vcc3v3>;
+	vcc-pf-supply = <&reg_vcc3v3>;
+	vcc-ph-supply = <&reg_vcc3v3>;
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pin>;
+	status = "okay";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1250000>;
+	regulator-max-microvolt = <1250000>;
+	regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+	status = "okay";
+};
+
+&reg_usb1_vbus {
+	status = "okay";
+};
+
+&reg_usb2_vbus {
+	status = "okay";
+};
+
+&tcon0_out {
+	tcon0_out_panel: endpoint@0 {
+		reg = <0>;
+		remote-endpoint = <&panel_input>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	usb2_vbus-supply = <&reg_usb2_vbus>;
+	status = "okay";
+};

arch/arm/dts/sun4i-a10.dtsi

@@ -115,13 +115,12 @@
 			reg = <0x0>;
 			clocks = <&ccu CLK_CPU>;
 			clock-latency = <244144>; /* 8 32k periods */
-			operating-points = <
+			operating-points =
 				/* kHz	  uV */
-				1008000 1400000
-				912000	1350000
-				864000	1300000
-				624000	1250000
-				>;
+				<1008000 1400000>,
+				<912000	1350000>,
+				<864000	1300000>,
+				<624000	1250000>;
 			#cooling-cells = <2>;
 		};
 	};
@@ -143,7 +142,7 @@
 			trips {
 				cpu_alert0: cpu-alert0 {
 					/* milliCelsius */
-					temperature = <850000>;
+					temperature = <85000>;
 					hysteresis = <2000>;
 					type = "passive";
 				};
@@ -184,14 +183,34 @@
 		status = "disabled";
 	};
 
+	pmu {
+		compatible = "arm,cortex-a8-pmu";
+		interrupts = <3>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+		default-pool {
+			compatible = "shared-dma-pool";
+			size = <0x6000000>;
+			alloc-ranges = <0x40000000 0x10000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
-		sram-controller@1c00000 {
-			compatible = "allwinner,sun4i-a10-sram-controller";
+		system-control@1c00000 {
+			compatible = "allwinner,sun4i-a10-system-control";
 			reg = <0x01c00000 0x30>;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -224,6 +243,19 @@
 					status = "disabled";
 				};
 			};
+
+			sram_c: sram@1d00000 {
+				compatible = "mmio-sram";
+				reg = <0x01d00000 0xd0000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x01d00000 0xd0000>;
+
+				ve_sram: sram-section@0 {
+					compatible = "allwinner,sun4i-a10-sram-c1";
+					reg = <0x000000 0x80000>;
+				};
+			};
 		};
 
 		dma: dma-controller@1c02000 {
@@ -234,7 +266,7 @@
 			#dma-cells = <2>;
 		};
 
-		nfc: nand@1c03000 {
+		nfc: nand-controller@1c03000 {
 			compatible = "allwinner,sun4i-a10-nand";
 			reg = <0x01c03000 0x1000>;
 			interrupts = <37>;
@@ -309,6 +341,7 @@
 				      "tcon-ch0",
 				      "tcon-ch1";
 			clock-output-names = "tcon0-pixel-clock";
+			#clock-cells = <0>;
 			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 
 			ports {
@@ -358,6 +391,7 @@
 				      "tcon-ch0",
 				      "tcon-ch1";
 			clock-output-names = "tcon1-pixel-clock";
+			#clock-cells = <0>;
 			dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 
 			ports {
@@ -394,6 +428,17 @@
 			};
 		};
 
+		video-codec@1c0e000 {
+			compatible = "allwinner,sun4i-a10-video-engine";
+			reg = <0x01c0e000 0x1000>;
+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+				 <&ccu CLK_DRAM_VE>;
+			clock-names = "ahb", "mod", "ram";
+			resets = <&ccu RST_VE>;
+			interrupts = <53>;
+			allwinner,sram = <&ve_sram 1>;
+		};
+
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun4i-a10-mmc";
 			reg = <0x01c0f000 0x1000>;
@@ -450,13 +495,14 @@
 			phy-names = "usb";
 			extcon = <&usbphy 0>;
 			allwinner,sram = <&otg_sram 1>;
+			dr_mode = "otg";
 			status = "disabled";
 		};
 
 		usbphy: phy@1c13400 {
 			#phy-cells = <1>;
 			compatible = "allwinner,sun4i-a10-usb-phy";
-			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+			reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 			reg-names = "phy_ctrl", "pmu1", "pmu2";
 			clocks = <&ccu CLK_USB_PHY>;
 			clock-names = "usb_phy";
@@ -530,8 +576,6 @@
 				};
 
 				hdmi_out: port@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
 					reg = <1>;
 				};
 			};
@@ -579,6 +623,16 @@
 			status = "disabled";
 		};
 
+		csi1: csi@1c1d000 {
+			compatible = "allwinner,sun4i-a10-csi1";
+			reg = <0x01c1d000 0x1000>;
+			interrupts = <43>;
+			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+			clock-names = "bus", "ram";
+			resets = <&ccu RST_CSI1>;
+			status = "disabled";
+		};
+
 		spi3: spi@1c1f000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c1f000 0x1000>;
@@ -625,6 +679,31 @@
 				function = "can";
 			};
 
+			/omit-if-no-ref/
+			csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+				pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+				       "PG6", "PG7", "PG8", "PG9", "PG10",
+				       "PG11";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+				       "PH5", "PH6", "PH7", "PH8", "PH9",
+				       "PH10", "PH11", "PH12", "PH13", "PH14",
+				       "PH15", "PH16", "PH17", "PH18", "PH19",
+				       "PH20", "PH21", "PH22", "PH23", "PH24",
+				       "PH25", "PH26", "PH27";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_clk_pg_pin: csi1-clk-pg-pin {
+				pins = "PG1";
+				function = "csi1";
+			};
+
 			emac_pins: emac0-pins {
 				pins = "PA0", "PA1", "PA2",
 				       "PA3", "PA4", "PA5", "PA6",
@@ -762,13 +841,20 @@
 		timer@1c20c00 {
 			compatible = "allwinner,sun4i-a10-timer";
 			reg = <0x01c20c00 0x90>;
-			interrupts = <22>;
+			interrupts = <22>,
+				     <23>,
+				     <24>,
+				     <25>,
+				     <67>,
+				     <68>;
 			clocks = <&osc24M>;
 		};
 
 		wdt: watchdog@1c20c90 {
 			compatible = "allwinner,sun4i-a10-wdt";
 			reg = <0x01c20c90 0x10>;
+			interrupts = <24>;
+			clocks = <&osc24M>;
 		};
 
 		rtc: rtc@1c20d00 {
@@ -1001,6 +1087,27 @@
 			status = "disabled";
 		};
 
+		mali: gpu@1c40000 {
+			compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
+			reg = <0x01c40000 0x10000>;
+			interrupts = <69>,
+				     <70>,
+				     <71>,
+				     <72>,
+				     <73>;
+			interrupt-names = "gp",
+					  "gpmmu",
+					  "pp0",
+					  "ppmmu0",
+					  "pmu";
+			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+			clock-names = "bus", "core";
+			resets = <&ccu RST_GPU>;
+
+			assigned-clocks = <&ccu CLK_GPU>;
+			assigned-clock-rates = <384000000>;
+		};
+
 		fe0: display-frontend@1e00000 {
 			compatible = "allwinner,sun4i-a10-display-frontend";
 			reg = <0x01e00000 0x20000>;

arch/arm/include/asm/arch-apple/rtkit.h

@@ -7,5 +7,23 @@
 #define APPLE_RTKIT_PWR_STATE_QUIESCED	0x10
 #define APPLE_RTKIT_PWR_STATE_ON	0x20
 
-int apple_rtkit_init(struct mbox_chan *);
-int apple_rtkit_shutdown(struct mbox_chan *, int);
+struct apple_rtkit_buffer {
+	void *buffer;
+	u64 dva;
+	size_t size;
+	bool is_mapped;
+};
+
+typedef int (*apple_rtkit_shmem_setup)(void *cookie,
+				       struct apple_rtkit_buffer *buf);
+typedef void (*apple_rtkit_shmem_destroy)(void *cookie,
+					  struct apple_rtkit_buffer *buf);
+
+struct apple_rtkit;
+
+struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie,
+				     apple_rtkit_shmem_setup shmem_setup,
+				     apple_rtkit_shmem_destroy shmem_destroy);
+void apple_rtkit_free(struct apple_rtkit *rtk);
+int apple_rtkit_boot(struct apple_rtkit *rtk);
+int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate);

arch/arm/include/asm/arch-apple/sart.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * The sart code is copied from m1n1 (https://github.com/AsahiLinux/m1n1) and
+ * licensed as MIT.
+ *
+ * (C) Copyright 2022 The Asahi Linux Contributors
+ */
+
+#ifndef SART_H
+#define SART_H
+
+#include <dm/ofnode.h>
+
+struct apple_sart;
+
+struct apple_sart *sart_init(ofnode node);
+void sart_free(struct apple_sart *sart);
+
+bool sart_add_allowed_region(struct apple_sart *sart, void *paddr, size_t sz);
+bool sart_remove_allowed_region(struct apple_sart *sart, void *paddr, size_t sz);
+
+#endif

arch/arm/mach-apple/Makefile

@@ -3,3 +3,4 @@
 obj-y += board.o
 obj-y += lowlevel_init.o
 obj-y += rtkit.o
+obj-$(CONFIG_NVME_APPLE) += sart.o

arch/arm/mach-apple/rtkit.c

@@ -17,6 +17,7 @@
 #define APPLE_RTKIT_EP_SYSLOG 2
 #define APPLE_RTKIT_EP_DEBUG 3
 #define APPLE_RTKIT_EP_IOREPORT 4
+#define APPLE_RTKIT_EP_TRACEKIT 10
 
 /* Messages for management endpoint. */
 #define APPLE_RTKIT_MGMT_TYPE GENMASK(59, 52)
@@ -51,7 +52,104 @@
 #define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK(51, 44)
 #define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK(41, 0)
 
-int apple_rtkit_init(struct mbox_chan *chan)
+#define TIMEOUT_1SEC_US 1000000
+
+struct apple_rtkit {
+	struct mbox_chan *chan;
+	void *cookie;
+	apple_rtkit_shmem_setup shmem_setup;
+	apple_rtkit_shmem_destroy shmem_destroy;
+
+	struct apple_rtkit_buffer syslog_buffer;
+	struct apple_rtkit_buffer crashlog_buffer;
+	struct apple_rtkit_buffer ioreport_buffer;
+};
+
+struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie,
+				     apple_rtkit_shmem_setup shmem_setup,
+				     apple_rtkit_shmem_destroy shmem_destroy)
+{
+	struct apple_rtkit *rtk;
+
+	rtk = calloc(sizeof(*rtk), 1);
+	if (!rtk)
+		return NULL;
+
+	rtk->chan = chan;
+	rtk->cookie = cookie;
+	rtk->shmem_setup = shmem_setup;
+	rtk->shmem_destroy = shmem_destroy;
+
+	return rtk;
+}
+
+void apple_rtkit_free(struct apple_rtkit *rtk)
+{
+	if (rtk->shmem_destroy) {
+		if (rtk->syslog_buffer.buffer)
+			rtk->shmem_destroy(rtk->cookie, &rtk->syslog_buffer);
+		if (rtk->crashlog_buffer.buffer)
+			rtk->shmem_destroy(rtk->cookie, &rtk->crashlog_buffer);
+		if (rtk->ioreport_buffer.buffer)
+			rtk->shmem_destroy(rtk->cookie, &rtk->ioreport_buffer);
+	}
+	free(rtk);
+}
+
+static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct apple_mbox_msg *msg)
+{
+	struct apple_rtkit_buffer *buf;
+	size_t num_4kpages;
+	int ret;
+
+	num_4kpages = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0);
+
+	if (num_4kpages == 0) {
+		printf("%s: unexpected request for buffer without size\n", __func__);
+		return -1;
+	}
+
+	switch (endpoint) {
+	case APPLE_RTKIT_EP_CRASHLOG:
+		buf = &rtk->crashlog_buffer;
+		break;
+	case APPLE_RTKIT_EP_SYSLOG:
+		buf = &rtk->syslog_buffer;
+		break;
+	case APPLE_RTKIT_EP_IOREPORT:
+		buf = &rtk->ioreport_buffer;
+		break;
+	default:
+		printf("%s: unexpected endpoint %d\n", __func__, endpoint);
+		return -1;
+	}
+
+	buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0);
+	buf->size = num_4kpages << 12;
+	buf->is_mapped = false;
+
+	if (rtk->shmem_setup) {
+		ret = rtk->shmem_setup(rtk->cookie, buf);
+		if (ret < 0) {
+			printf("%s: shmen_setup failed for endpoint %d\n", __func__,
+			       endpoint);
+			return ret;
+		}
+	}
+
+	if (!buf->is_mapped) {
+		msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) |
+				FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, num_4kpages) |
+				FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva);
+		msg->msg1 = endpoint;
+
+		return mbox_send(rtk->chan, msg);
+	}
+
+	return 0;
+}
+
+int apple_rtkit_boot(struct apple_rtkit *rtk)
 {
 	struct apple_mbox_msg msg;
 	int endpoints[256];
@@ -67,12 +165,12 @@ int apple_rtkit_init(struct mbox_chan *chan)
 	msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
 		FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON);
 	msg.msg1 = APPLE_RTKIT_EP_MGMT;
-	ret = mbox_send(chan, &msg);
+	ret = mbox_send(rtk->chan, &msg);
 	if (ret < 0)
 		return ret;
 
 	/* Wait for protocol version negotiation message. */
-	ret = mbox_recv(chan, &msg, 10000);
+	ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
 	if (ret < 0)
 		return ret;
 
@@ -108,13 +206,13 @@ int apple_rtkit_init(struct mbox_chan *chan)
 		FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MINVER, want_ver) |
 		FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MAXVER, want_ver);
 	msg.msg1 = APPLE_RTKIT_EP_MGMT;
-	ret = mbox_send(chan, &msg);
+	ret = mbox_send(rtk->chan, &msg);
 	if (ret < 0)
 		return ret;
 
 wait_epmap:
 	/* Wait for endpoint map message. */
-	ret = mbox_recv(chan, &msg, 10000);
+	ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
 	if (ret < 0)
 		return ret;
 
@@ -145,7 +243,7 @@ wait_epmap:
 		reply |= APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE;
 	msg.msg0 = reply;
 	msg.msg1 = APPLE_RTKIT_EP_MGMT;
-	ret = mbox_send(chan, &msg);
+	ret = mbox_send(rtk->chan, &msg);
 	if (ret < 0)
 		return ret;
 
@@ -153,24 +251,33 @@ wait_epmap:
 		goto wait_epmap;
 
 	for (i = 0; i < nendpoints; i++) {
-		/* Don't start the syslog endpoint since we can't
-		   easily handle its messages in U-Boot. */
-		if (endpoints[i] == APPLE_RTKIT_EP_SYSLOG)
+		/* Start only necessary endpoints. The syslog endpoint is
+		 * particularly noisy and its message can't easily be handled
+		 * within U-Boot.
+		 */
+		switch (endpoints[i]) {
+		case APPLE_RTKIT_EP_MGMT:
+		case APPLE_RTKIT_EP_SYSLOG:
+		case APPLE_RTKIT_EP_DEBUG:
+		case APPLE_RTKIT_EP_TRACEKIT:
 			continue;
+		default:
+			break;
+		}
 
 		/* Request endpoint. */
 		msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_STARTEP) |
 			FIELD_PREP(APPLE_RTKIT_MGMT_STARTEP_EP, endpoints[i]) |
 			APPLE_RTKIT_MGMT_STARTEP_FLAG;
 		msg.msg1 = APPLE_RTKIT_EP_MGMT;
-		ret = mbox_send(chan, &msg);
+		ret = mbox_send(rtk->chan, &msg);
 		if (ret < 0)
 			return ret;
 	}
 
 	pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
 	while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
-		ret = mbox_recv(chan, &msg, 1000000);
+		ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
 		if (ret < 0)
 			return ret;
 
@@ -180,21 +287,23 @@ wait_epmap:
 		if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
 		    endpoint == APPLE_RTKIT_EP_SYSLOG ||
 		    endpoint == APPLE_RTKIT_EP_IOREPORT) {
-			u64 addr = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg.msg0);
-			u64 size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg.msg0);
-
-			if (msgtype == APPLE_RTKIT_BUFFER_REQUEST && addr != 0)
-				continue;
-
-			msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) |
-				FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, size) |
-				FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, addr);
-			msg.msg1 = endpoint;
-			ret = mbox_send(chan, &msg);
+			if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) {
+				ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
 				if (ret < 0)
 					return ret;
 				continue;
 			}
+		}
+
+		if (endpoint == APPLE_RTKIT_EP_IOREPORT) {
+			// these two messages have to be ack-ed for proper startup
+			if (msgtype == 0xc || msgtype == 0x8) {
+				ret = mbox_send(rtk->chan, &msg);
+				if (ret < 0)
+					return ret;
+				continue;
+			}
+		}
 
 		if (endpoint != APPLE_RTKIT_EP_MGMT) {
 			printf("%s: unexpected endpoint %d\n", __func__, endpoint);
@@ -211,7 +320,7 @@ wait_epmap:
 	return 0;
 }
 
-int apple_rtkit_shutdown(struct mbox_chan *chan, int pwrstate)
+int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate)
 {
 	struct apple_mbox_msg msg;
 	int ret;
@@ -219,11 +328,11 @@ int apple_rtkit_shutdown(struct mbox_chan *chan, int pwrstate)
 	msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
 		FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
 	msg.msg1 = APPLE_RTKIT_EP_MGMT;
-	ret = mbox_send(chan, &msg);
+	ret = mbox_send(rtk->chan, &msg);
 	if (ret < 0)
 		return ret;
 
-	ret = mbox_recv(chan, &msg, 100000);
+	ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
 	if (ret < 0)
 		return ret;
 

arch/arm/mach-apple/sart.c

@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: MIT
+/*
+ * The sart code is copied from m1n1 (https://github.com/AsahiLinux/m1n1) and
+ * licensed as MIT.
+ *
+ * (C) Copyright 2022 The Asahi Linux Contributors
+ */
+
+#include <asm/io.h>
+#include <asm/arch/sart.h>
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+#include <malloc.h>
+
+#define APPLE_SART_MAX_ENTRIES 16
+
+/* This is probably a bitfield but the exact meaning of each bit is unknown. */
+#define APPLE_SART_FLAGS_ALLOW 0xff
+
+/* SARTv2 registers */
+#define APPLE_SART2_CONFIG(idx)       (0x00 + 4 * (idx))
+#define APPLE_SART2_CONFIG_FLAGS      GENMASK(31, 24)
+#define APPLE_SART2_CONFIG_SIZE       GENMASK(23, 0)
+#define APPLE_SART2_CONFIG_SIZE_SHIFT 12
+#define APPLE_SART2_CONFIG_SIZE_MAX   GENMASK(23, 0)
+
+#define APPLE_SART2_PADDR(idx)  (0x40 + 4 * (idx))
+#define APPLE_SART2_PADDR_SHIFT 12
+
+/* SARTv3 registers */
+#define APPLE_SART3_CONFIG(idx) (0x00 + 4 * (idx))
+
+#define APPLE_SART3_PADDR(idx)  (0x40 + 4 * (idx))
+#define APPLE_SART3_PADDR_SHIFT 12
+
+#define APPLE_SART3_SIZE(idx)  (0x80 + 4 * (idx))
+#define APPLE_SART3_SIZE_SHIFT 12
+#define APPLE_SART3_SIZE_MAX   GENMASK(29, 0)
+
+struct apple_sart {
+	uintptr_t base;
+	u32 protected_entries;
+
+	void (*get_entry)(struct apple_sart *sart, int index, u8 *flags, void **paddr,
+			  size_t *size);
+	bool (*set_entry)(struct apple_sart *sart, int index, u8 flags, void *paddr,
+			  size_t size);
+};
+
+static void sart2_get_entry(struct apple_sart *sart, int index, u8 *flags, void **paddr,
+			    size_t *size)
+{
+	u32 cfg = readl(sart->base + APPLE_SART2_CONFIG(index));
+	*flags = FIELD_GET(APPLE_SART2_CONFIG_FLAGS, cfg);
+	*size = (size_t)FIELD_GET(APPLE_SART2_CONFIG_SIZE, cfg) << APPLE_SART2_CONFIG_SIZE_SHIFT;
+	*paddr = (void *)
+		((u64)readl(sart->base + APPLE_SART2_PADDR(index)) << APPLE_SART2_PADDR_SHIFT);
+}
+
+static bool sart2_set_entry(struct apple_sart *sart, int index, u8 flags, void *paddr_,
+			    size_t size)
+{
+	u32 cfg;
+	u64 paddr = (u64)paddr_;
+
+	if (size & ((1 << APPLE_SART2_CONFIG_SIZE_SHIFT) - 1))
+		return false;
+	if (paddr & ((1 << APPLE_SART2_PADDR_SHIFT) - 1))
+		return false;
+
+	size >>= APPLE_SART2_CONFIG_SIZE_SHIFT;
+	paddr >>= APPLE_SART2_PADDR_SHIFT;
+
+	if (size > APPLE_SART2_CONFIG_SIZE_MAX)
+		return false;
+
+	cfg = FIELD_PREP(APPLE_SART2_CONFIG_FLAGS, flags);
+	cfg |= FIELD_PREP(APPLE_SART2_CONFIG_SIZE, size);
+
+	writel(paddr, sart->base + APPLE_SART2_PADDR(index));
+	writel(cfg, sart->base + APPLE_SART2_CONFIG(index));
+
+	return true;
+}
+
+static void sart3_get_entry(struct apple_sart *sart, int index, u8 *flags, void **paddr,
+			    size_t *size)
+{
+	*flags = readl(sart->base + APPLE_SART3_CONFIG(index));
+	*size = (size_t)readl(sart->base + APPLE_SART3_SIZE(index)) << APPLE_SART3_SIZE_SHIFT;
+	*paddr = (void *)
+		((u64)readl(sart->base + APPLE_SART3_PADDR(index)) << APPLE_SART3_PADDR_SHIFT);
+}
+
+static bool sart3_set_entry(struct apple_sart *sart, int index, u8 flags, void *paddr_,
+			    size_t size)
+{
+	u64 paddr = (u64)paddr_;
+
+	if (size & ((1 << APPLE_SART3_SIZE_SHIFT) - 1))
+		return false;
+	if (paddr & ((1 << APPLE_SART3_PADDR_SHIFT) - 1))
+		return false;
+
+	paddr >>= APPLE_SART3_PADDR_SHIFT;
+	size >>= APPLE_SART3_SIZE_SHIFT;
+
+	if (size > APPLE_SART3_SIZE_MAX)
+		return false;
+
+	writel(paddr, sart->base + APPLE_SART3_PADDR(index));
+	writel(size, sart->base + APPLE_SART3_SIZE(index));
+	writel(flags, sart->base + APPLE_SART3_CONFIG(index));
+
+	return true;
+}
+
+struct apple_sart *sart_init(ofnode node)
+{
+	phys_addr_t base;
+	u32 sart_version;
+	struct apple_sart *sart;
+
+	base = ofnode_get_addr(node);
+	if (base == FDT_ADDR_T_NONE)
+		return NULL;
+
+	if (ofnode_device_is_compatible(node, "apple,t8103-sart")) {
+		sart_version = 2;
+	} else if (ofnode_device_is_compatible(node, "apple,t6000-sart")) {
+		sart_version = 3;
+	} else {
+		printf("sart: unknown SART compatible: %sd\n",
+		       ofnode_read_string(node, "compatible"));
+		return NULL;
+	}
+
+	sart = calloc(sizeof(*sart), 1);
+	if (!sart)
+		return NULL;
+
+	sart->base = base;
+
+	switch (sart_version) {
+	case 2:
+		sart->get_entry = sart2_get_entry;
+		sart->set_entry = sart2_set_entry;
+		break;
+	case 3:
+		sart->get_entry = sart3_get_entry;
+		sart->set_entry = sart3_set_entry;
+		break;
+	default:
+		printf("sart: SART has unknown version %d\n", sart_version);
+		free(sart);
+		return NULL;
+	}
+
+	sart->protected_entries = 0;
+	for (unsigned int i = 0; i < APPLE_SART_MAX_ENTRIES; ++i) {
+		void *paddr;
+		u8 flags;
+		size_t sz;
+
+		sart->get_entry(sart, i, &flags, &paddr, &sz);
+		if (flags)
+			sart->protected_entries |= 1 << i;
+	}
+
+	return sart;
+}
+
+void sart_free(struct apple_sart *sart)
+{
+	for (unsigned int i = 0; i < APPLE_SART_MAX_ENTRIES; ++i) {
+		if (sart->protected_entries & (1 << i))
+			continue;
+		sart->set_entry(sart, i, 0, NULL, 0);
+	}
+
+	free(sart);
+}
+
+bool sart_add_allowed_region(struct apple_sart *sart, void *paddr, size_t sz)
+{
+	for (unsigned int i = 0; i < APPLE_SART_MAX_ENTRIES; ++i) {
+		void *e_paddr;
+		u8 e_flags;
+		size_t e_sz;
+
+		if (sart->protected_entries & (1 << i))
+			continue;
+
+		sart->get_entry(sart, i, &e_flags, &e_paddr, &e_sz);
+		if (e_flags)
+			continue;
+
+		return sart->set_entry(sart, i, APPLE_SART_FLAGS_ALLOW, paddr, sz);
+	}
+
+	printf("sart: no more free entries\n");
+	return false;
+}
+
+bool sart_remove_allowed_region(struct apple_sart *sart, void *paddr, size_t sz)
+{
+	for (unsigned int i = 0; i < APPLE_SART_MAX_ENTRIES; ++i) {
+		void *e_paddr;
+		u8 e_flags;
+		size_t e_sz;
+
+		if (sart->protected_entries & (1 << i))
+			continue;
+
+		sart->get_entry(sart, i, &e_flags, &e_paddr, &e_sz);
+		if (!e_flags)
+			continue;
+		if (e_paddr != paddr)
+			continue;
+		if (e_sz != sz)
+			continue;
+
+		return sart->set_entry(sart, i, 0, NULL, 0);
+	}
+
+	printf("sart: could not find entry to be removed\n");
+	return false;
+}

arch/arm/mach-imx/imx8m/Kconfig

@@ -107,6 +107,9 @@ config TARGET_KONTRON_MX8MM
 	select IMX8MM
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MN_BSH_SMM_S2
 	bool "imx8mn-bsh-smm-s2"

arch/arm/mach-imx/imx8m/soc.c

@@ -1203,6 +1203,48 @@ static int cleanup_nodes_for_efi(void *blob)
 	return 0;
 }
 
+static int fixup_thermal_trips(void *blob, const char *name)
+{
+	int minc, maxc;
+	int node, trip;
+
+	node = fdt_path_offset(blob, "/thermal-zones");
+	if (node < 0)
+		return node;
+
+	node = fdt_subnode_offset(blob, node, name);
+	if (node < 0)
+		return node;
+
+	node = fdt_subnode_offset(blob, node, "trips");
+	if (node < 0)
+		return node;
+
+	get_cpu_temp_grade(&minc, &maxc);
+
+	fdt_for_each_subnode(trip, blob, node) {
+		const char *type;
+		int temp, ret;
+
+		type = fdt_getprop(blob, trip, "type", NULL);
+		if (!type)
+			continue;
+
+		temp = 0;
+		if (!strcmp(type, "critical"))
+			temp = 1000 * maxc;
+		else if (!strcmp(type, "passive"))
+			temp = 1000 * (maxc - 10);
+		if (temp) {
+			ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
 int ft_system_setup(void *blob, struct bd_info *bd)
 {
 #ifdef CONFIG_IMX8MQ
@@ -1345,6 +1387,13 @@ usb_modify_speed:
 #endif
 
 	cleanup_nodes_for_efi(blob);
+
+	if (fixup_thermal_trips(blob, "cpu-thermal"))
+		printf("Failed to update cpu-thermal trip(s)");
+	if (IS_ENABLED(CONFIG_IMX8MP) &&
+	    fixup_thermal_trips(blob, "soc-thermal"))
+		printf("Failed to update soc-thermal trip(s)");
+
 	return 0;
 }
 #endif

arch/arm/mach-imx/mx6/ddr.c

@@ -1469,8 +1469,17 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mprddqby3dl, 0x33333333);
 	}
 
-	/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
-	val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+	/*
+	 * MMDC Termination: rtt_nom:2 RZQ/2(120ohm),
+	 *                   rtt_nom:1 RZQ/4(60ohm),
+	 *                   rtt_nom:0 Disabled
+	 */
+	if (sysinfo->rtt_nom == 0)
+		val = 0x00000000;
+	else if (sysinfo->rtt_nom == 2)
+		val = 0x00011117;
+	else
+		val = 0x00022227;
 	mmdc0->mpodtctrl = val;
 	if (sysinfo->dsize > 1)
 		MMDC1(mpodtctrl, val);

arch/arm/mach-meson/board-axg.c

@@ -106,7 +106,7 @@ int board_usb_init(int index, enum usb_init_type init)
 
 	/* find the usb glue node */
 	node = fdt_node_offset_by_compatible(blob, -1,
-					     "amlogic,meson-gxl-usb-ctrl");
+					     "amlogic,meson-axg-usb-ctrl");
 	if (node < 0) {
 		debug("Not found usb-control node\n");
 		return -ENODEV;
@@ -192,7 +192,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 
 	/* find the usb glue node */
 	node = fdt_node_offset_by_compatible(blob, -1,
-					     "amlogic,meson-gxl-usb-ctrl");
+					     "amlogic,meson-axg-usb-ctrl");
 	if (node < 0) {
 		debug("Not found usb-control node\n");
 		return -ENODEV;

arch/arm/mach-rockchip/Kconfig

@@ -361,6 +361,16 @@ config ROCKCHIP_BOOT_MODE_REG
 	  The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
 	  according to the value from this register.
 
+config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
+	bool "Disable device boot on power plug-in"
+	depends on PMIC_RK8XX
+	default n
+	---help---
+	  Say Y here to prevent the device from booting up because of a plug-in
+	  event. When set, the device will boot briefly to determine why it was
+	  powered on, and if it was determined because of a plug-in event
+	  instead of a button press event it will shut back off.
+
 config ROCKCHIP_STIMER
 	bool "Rockchip STIMER support"
 	default y

arch/arm/mach-rockchip/board.c

@@ -90,7 +90,7 @@ int board_usb_init(int index, enum usb_init_type init)
 	}
 	otg_data.regs_otg = ofnode_get_addr(node);
 
-#ifdef CONFIG_ROCKCHIP_RK3288
+#ifdef CONFIG_ROCKCHIP_USB2_PHY
 	int ret;
 	u32 phandle, offset;
 	ofnode phy_node;

arch/arm/mach-rockchip/make_fit_atf.py

@@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, tee_file_name, dtbs_file
     num_segments = len(segments)
 
     if tee_file_name:
-        tee_segments = unpack_elf(tee_file_name)
+        tee_segments = unpack_tee_file(tee_file_name)
         for index, entry, paddr, data in tee_segments:
             append_tee_node(fit_file, num_segments + index + 1, paddr, entry)
         num_segments = num_segments + len(tee_segments)
@@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name):
 
 def generate_tee_binary(tee_file_name):
     if tee_file_name:
-        for index, entry, paddr, data in unpack_elf(tee_file_name):
+        for index, entry, paddr, data in unpack_tee_file(tee_file_name):
             file_name = 'tee_0x%08x.bin' % paddr
             with open(file_name, "wb") as atf:
                 atf.write(data)
@@ -194,6 +194,31 @@ def unpack_elf(filename):
                 segments.append((index, e_entry, p_paddr, p_data))
     return segments
 
+def unpack_tee_file(filename):
+    if filename.endswith('.elf'):
+        return unpack_elf(filename)
+    with open(filename, 'rb') as file:
+        bin = file.read()
+    segments = []
+    if bin[0:5] == b'OPTE\x01':
+        # OP-TEE v1 format (tee.bin)
+        init_sz, start_hi, start_lo, _, paged_sz = struct.unpack_from('<5I',
+                                                                      bin,
+                                                                      0x8)
+        if paged_sz != 0:
+            raise ValueError("OP-TEE paged mode not supported")
+        e_entry = (start_hi << 32) + start_lo
+        p_addr = e_entry
+        p_data = bin[0x1c:]
+        if len(p_data) != init_sz:
+            raise ValueError("Invalid file '%s': size mismatch "
+                             "(expected %d, have %d)" % (filename, init_sz,
+                                                         len(p_data)))
+        segments.append((0, e_entry, p_addr, p_data))
+    else:
+        raise ValueError("Unknown format for TEE file '%s'" % filename)
+    return segments
+
 def main():
     uboot_elf = "./u-boot"
     fit_its = sys.stdout
@@ -210,11 +235,13 @@ def main():
         logging.warning(' Please read Building section in doc/README.rockchip')
 
     if "TEE" in os.environ:
-        tee_elf = os.getenv("TEE")
+        tee_file = os.getenv("TEE")
+    elif os.path.isfile("./tee.bin"):
+        tee_file = "./tee.bin"
     elif os.path.isfile("./tee.elf"):
-        tee_elf = "./tee.elf"
+        tee_file = "./tee.elf"
     else:
-        tee_elf = ""
+        tee_file = ""
 
     opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h")
     for opt, val in opts:
@@ -225,16 +252,16 @@ def main():
         elif opt == "-b":
             bl31_elf = val
         elif opt == "-t":
-            tee_elf = val
+            tee_file = val
         elif opt == "-h":
             print(__doc__)
             sys.exit(2)
 
     dtbs = args
 
-    generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs)
+    generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs)
     generate_atf_binary(bl31_elf)
-    generate_tee_binary(tee_elf)
+    generate_tee_binary(tee_file)
 
 if __name__ == "__main__":
     main()

arch/arm/mach-socfpga/Kconfig

@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Arria V)"
 	select TARGET_SOCFPGA_ARRIA5
 
+config TARGET_SOCFPGA_CHAMELEONV3
+	bool "Google Chameleon v3 (Arria 10)"
+	select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -198,6 +202,7 @@ config SYS_BOARD
 	default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -224,6 +229,7 @@ config SYS_VENDOR
 	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "google" if TARGET_SOCFPGA_CHAMELEONV3
 	default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
 	default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -240,6 +246,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO

arch/arm/mach-socfpga/clock_manager_arria10.c

@@ -15,6 +15,10 @@
 
 #ifdef CONFIG_SPL_BUILD
 
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound);
+
 static u32 eosc1_hz;
 static u32 cb_intosc_hz;
 static u32 f2s_free_hz;
@@ -551,13 +555,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
 			CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 			cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
 			socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-		mdelay(1);
+		sdelay(1000000); /* 1ms */
 		cm_wait_for_lock(LOCKED_MASK);
 	}
 	writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 		main_cfg->vco1_numer,
 		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-	mdelay(1);
+	sdelay(1000000); /* 1ms */
 	cm_wait_for_lock(LOCKED_MASK);
 }
 
@@ -585,16 +589,25 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
 						     clk_hz),
 			      socfpga_get_clkmgr_addr() +
 			      CLKMGR_A10_PERPLL_VCO1);
-		mdelay(1);
+		sdelay(1000000); /* 1ms */
 		cm_wait_for_lock(LOCKED_MASK);
 	}
 	writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 		      per_cfg->vco1_numer,
 		      socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
-	mdelay(1);
+	sdelay(1000000); /* 1ms */
 	cm_wait_for_lock(LOCKED_MASK);
 }
 
+/* function to poll in the fsm busy bit */
+static int cm_busy_wait_for_fsm(void)
+{
+	void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+	/* 20s timeout */
+	return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 100000000);
+}
+
 /*
  * Setup clocks while making no assumptions of the
  * previous state of the clocks.
@@ -727,7 +740,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 			socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
 	/* Wait for at least 5 us */
-	udelay(5);
+	sdelay(5000);
 
 	/* Now deassert BGPWRDN and PWRDN */
 	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +751,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 		     CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 
 	/* Wait for at least 7 us */
-	udelay(7);
+	sdelay(7000);
 
 	/* enable the VCO and disable the external regulator to PLL */
 	writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
@@ -878,19 +891,19 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 	writel(CLKMGR_MAINPLL_BYPASS_RESET,
 	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
 	/* wait till Clock Manager is not busy */
-	cm_wait_for_fsm();
+	cm_busy_wait_for_fsm();
 
 	/* release perpll from bypass */
 	writel(CLKMGR_PERPLL_BYPASS_RESET,
 	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
 	/* wait till Clock Manager is not busy */
-	cm_wait_for_fsm();
+	cm_busy_wait_for_fsm();
 
 	/* clear boot mode */
 	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 		     CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
 	/* wait till Clock Manager is not busy */
-	cm_wait_for_fsm();
+	cm_busy_wait_for_fsm();
 
 	/* At here, we need to ramp to final value if needed */
 	if (pll_ramp_main_hz != 0)

arch/arm/mach-socfpga/misc_arria10.c

@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
 	return 0;
 }
 #endif
+
+void dram_bank_mmu_setup(int bank)
+{
+	struct bd_info *bd = gd->bd;
+	u32 start, size;
+	int i;
+
+	/* If we're still in OCRAM, don't set the XN bit on it */
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		set_section_dcache(
+			CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+			DCACHE_WRITETHROUGH);
+	}
+
+	/*
+	 * The default implementation of this function allows the DRAM dcache
+	 * to be enabled only after relocation. However, to speed up ECC
+	 * initialization, we want to be able to enable DRAM dcache before
+	 * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+	 * is set first).
+	 */
+	start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+	size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+	for (i = start; i < start + size; i++)
+		set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}

arch/sandbox/include/asm/sdl.h

@@ -94,6 +94,11 @@ static inline int sandbox_sdl_init_display(int width, int height, int log2_bpp,
 	return -ENODEV;
 }
 
+static inline int sandbox_sdl_remove_display(void)
+{
+	return -ENODEV;
+}
+
 static inline int sandbox_sdl_sync(void *lcd_base)
 {
 	return -ENODEV;

board/BuR/brppt1/MAINTAINERS

@@ -1,5 +1,5 @@
 BRPPT1 BOARD
-M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brppt1/
 F:	include/configs/brppt1.h

board/BuR/brppt2/MAINTAINERS

@@ -1,5 +1,5 @@
 BUR_PPT2 BOARD
-M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brppt2/
 F:	include/configs/brppt2.h

board/BuR/brsmarc1/MAINTAINERS

@@ -1,5 +1,5 @@
 BRSMARC1 BOARD
-M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brsmarc1/
 F:	include/configs/brsmarc1.h

board/BuR/brxre1/MAINTAINERS

@@ -1,5 +1,5 @@
 BRXRE1 BOARD
-M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
 S:	Maintained
 F:	board/BuR/brxre1/
 F:	include/configs/brxre1.h

board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c

@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <dm.h>
+#include <dm/device-internal.h>
 #include <i2c_eeprom.h>
 #include <malloc.h>
 #include <net.h>
@@ -104,7 +105,15 @@ int board_init(void)
 
 int board_late_init(void)
 {
+	struct udevice *dev;
+	int ret;
+
 	setup_boot_device();
 	setup_mac_address();
+
+	ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev);
+	if (ret)
+		printf("Error bringing up USB hub (%d)\n", ret);
+
 	return 0;
 }

board/google/chameleonv3/MAINTAINERS

@@ -0,0 +1,6 @@
+CHAMELEONV3 BOARD
+M:	Paweł Anikiel <pan@semihalf.com>
+S:	Maintained
+F:	board/google/chameleonv3/
+F:	include/configs/socfpga_chameleonv3.h
+F:	configs/socfpga_chameleonv3_defconfig

board/google/chameleonv3/Makefile

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y	:= board.o mercury_aa1.o

board/google/chameleonv3/board.c

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include <net.h>
+#include <errno.h>
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+	u8 mac[ARP_HLEN];
+	int res;
+
+	if (env_get("ethaddr"))
+		return 0;
+
+	res = mercury_aa1_read_mac(mac);
+	if (res) {
+		printf("couldn't read mac address: %s\n", errno_str(res));
+		return 0;
+	}
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("ethaddr", mac);
+
+	return 0;
+}

board/google/chameleonv3/fpga.its

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA full bitstream";
+			data = /incbin/("../../../fpga.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA config";
+			fpga = "fpga-periph-1";
+		};
+	};
+};

board/google/chameleonv3/fpga_early_io.its

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA peripheral bitstream";
+			data = /incbin/("../../../periph.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+		fpga-core-1 {
+			description = "FPGA core bitstream";
+			data = /incbin/("../../../core.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA config";
+			fpga = "fpga-periph-1", "fpga-core-1";
+		};
+	};
+};

board/google/chameleonv3/mercury_aa1.c

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include <net.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <atsha204a-i2c.h>
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+	struct udevice *dev;
+	u8 buf[8];
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev);
+	if (ret)
+		return ret;
+
+	ret = atsha204a_wakeup(dev);
+	if (ret)
+		return ret;
+
+	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     MERCURY_AA1_ATSHA204A_OTP_MAC0, buf);
+	if (ret)
+		goto sleep;
+
+	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     MERCURY_AA1_ATSHA204A_OTP_MAC1, buf + 4);
+	if (ret)
+		goto sleep;
+
+	memcpy(mac, buf, ARP_HLEN);
+
+sleep:
+	atsha204a_sleep(dev);
+	return ret;
+}

board/google/chameleonv3/mercury_aa1.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/**
+ * mercury_aa1_read_mac() - Read mac address from on-board OTP memory
+ *
+ * @mac: Returned mac address
+ * Return: 0 if successful, -ve on error
+ */
+int mercury_aa1_read_mac(u8 *mac);

board/kontron/sl-mx8mm/spl.c

@@ -13,6 +13,9 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
 #include <hang.h>
 #include <i2c.h>
 #include <init.h>
@@ -213,6 +216,12 @@ void spl_board_init(void)
 	struct udevice *dev;
 	int ret;
 
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize %s: %d\n", dev->name, ret);
+	}
+
 	puts("Normal Boot\n");
 
 	ret = uclass_get_device_by_name(UCLASS_CLK,

board/sunxi/board.c

@@ -128,26 +128,37 @@ void i2c_init_board(void)
  * Try to use the environment from the boot source first.
  * For MMC, this means a FAT partition on the boot device (SD or eMMC).
  * If the raw MMC environment is also enabled, this is tried next.
+ * When booting from NAND we try UBI first, then NAND directly.
  * SPI flash falls back to FAT (on SD card).
  */
 enum env_location env_get_location(enum env_operation op, int prio)
 {
-	enum env_location boot_loc = ENVL_FAT;
+	if (prio > 1)
+		return ENVL_UNKNOWN;
 
-	gd->env_load_prio = prio;
+	/* NOWHERE is exclusive, no other option can be defined. */
+	if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+		return ENVL_NOWHERE;
 
 	switch (sunxi_get_boot_device()) {
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
-		boot_loc = ENVL_FAT;
+		if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+			return ENVL_MMC;
 		break;
 	case BOOT_DEVICE_NAND:
+		if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
 		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
-			boot_loc = ENVL_NAND;
+			return ENVL_NAND;
 		break;
 	case BOOT_DEVICE_SPI:
-		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
-			boot_loc = ENVL_SPI_FLASH;
+		if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
 		break;
 	case BOOT_DEVICE_BOARD:
 		break;
@@ -155,21 +166,19 @@ enum env_location env_get_location(enum env_operation op, int prio)
 		break;
 	}
 
-	/* Always try to access the environment on the boot device first. */
-	if (prio == 0)
-		return boot_loc;
-
-	if (prio == 1) {
-		switch (boot_loc) {
-		case ENVL_SPI_FLASH:
+	/*
+	 * If we come here for the first time, we *must* return a valid
+	 * environment location other than ENVL_UNKNOWN, or the setup sequence
+	 * in board_f() will silently hang. This is arguably a bug in
+	 * env_init(), but for now pick one environment for which we know for
+	 * sure to have a driver for. For all defconfigs this is either FAT
+	 * or UBI, or NOWHERE, which is already handled above.
+	 */
+	if (prio == 0) {
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
 			return ENVL_FAT;
-		case ENVL_FAT:
-			if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
-				return ENVL_MMC;
-			break;
-		default:
-			break;
-		}
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
 	}
 
 	return ENVL_UNKNOWN;

board/toradex/apalis_imx6/apalis_imx6.c

@@ -771,244 +771,6 @@ void ldo_mode_set(int ldo_bypass)
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
 
-static int mx6_com_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR	con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x128mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x555A7954,
-MX6_MMDC_P0_MDCFG1, 0xDB328F64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x005A1023,
-MX6_MMDC_P0_MDOTC, 0x09555050,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000027,
-MX6_MMDC_P0_MDCTL, 0x831A0000,
-MX6_MMDC_P0_MDSCR, 0x04088032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00428031,
-MX6_MMDC_P0_MDSCR, 0x19308030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00005800,
-MX6_MMDC_P0_MPODTCTRL, 0x00000000,
-MX6_MMDC_P1_MPODTCTRL, 0x00000000,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
-MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
-MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
-MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
-MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-static int mx6_it_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR	con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x256mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x898E78f5,
-MX6_MMDC_P0_MDCFG1, 0xff328f64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x008E1023,
-MX6_MMDC_P0_MDOTC, 0x09444040,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000047,
-MX6_MMDC_P0_MDCTL, 0x841A0000,
-MX6_MMDC_P0_MDSCR, 0x02888032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00048031,
-MX6_MMDC_P0_MDSCR, 0x19408030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00007800,
-MX6_MMDC_P0_MPODTCTRL, 0x00022227,
-MX6_MMDC_P1_MPODTCTRL, 0x00022227,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
-MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
-MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
-MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
-MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -1024,36 +786,198 @@ static void ccgr_init(void)
 /*
  * Setup CCM_CCOSR register as follows:
  *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
+ * clko2_en  = 1     --> CKO2 enabled
+ * clko2_div = 000   --> divide by 1
+ * clko2_sel = 01110 --> osc_clk (24MHz)
  *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ * clk_out_sel = 1   --> Output CKO2 to CKO1
+ *
+ * This sets both CLKO2/CLKO1 output to 24MHz,
+ * CLKO1 configuration not relevant because of clk_out_sel
+ * (CLKO1 set to default)
  */
-	writel(0x000000FB, &ccm->ccosr);
+	writel(0x010E0101, &ccm->ccosr);
 }
 
-static void ddr_init(int *table, int size)
-{
-	int i;
 
-	for (i = 0; i < size / 2 ; i++)
-		writel(table[2 * i + 1], table[2 * i]);
-}
+#define PAD_CTL_INPUT_DDR BIT(17)
+
+struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	/* Differential input, 40 ohm DSE */
+	.dram_sdclk_0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_sdclk_1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_cas = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_ras = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_reset = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+
+	/* SDKE[0:1]: BIT(12) and BIT(13) are reserved and set at reset */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+
+	.dram_sdba2 = 0x00000000,
+
+	/* ODT[0:1]: 40 ohm DSE, BIT(12) and BIT(13) are reserved and set at reset */
+	.dram_sdodt0 = PAD_CTL_DSE_40ohm | 0x00003000,
+	.dram_sdodt1 = PAD_CTL_DSE_40ohm | 0x00003000,
+
+	/* SDQS[0:7]: 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
+	.dram_sdqs0 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs1 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs2 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs3 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs4 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs5 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs6 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs7 = PAD_CTL_DSE_40ohm,
+
+	/* DQM[0:7]: Differential input, 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
+	.dram_dqm0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm2 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm3 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm4 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm5 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm6 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm7 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+};
+
+struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = 0x000C0000,
+
+	/* SDQS[0:7]: Differential input */
+	.grp_ddrmode_ctl = PAD_CTL_INPUT_DDR,
+
+	/* DATA[0:63]: Pull/Keeper disabled */
+	.grp_ddrpke = 0,
+
+	/* ADDR[0:16], SDBA[0:1]: 40 ohm DSE */
+	.grp_addds = PAD_CTL_DSE_40ohm,
+
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm DSE */
+	.grp_ctlds = PAD_CTL_DSE_40ohm,
+
+	/* DATA[0:63]: Differential input */
+	.grp_ddrmode = PAD_CTL_INPUT_DDR,
+
+	/* DATA[0:63]: 40 ohm DSE */
+	.grp_b0ds = PAD_CTL_DSE_40ohm,
+	.grp_b1ds = PAD_CTL_DSE_40ohm,
+	.grp_b2ds = PAD_CTL_DSE_40ohm,
+	.grp_b3ds = PAD_CTL_DSE_40ohm,
+	.grp_b4ds = PAD_CTL_DSE_40ohm,
+	.grp_b5ds = PAD_CTL_DSE_40ohm,
+	.grp_b6ds = PAD_CTL_DSE_40ohm,
+	.grp_b7ds = PAD_CTL_DSE_40ohm,
+};
+
+struct mx6_ddr_sysinfo sysinfo = {
+	.dsize = 2,         /* width of data bus: 2=64 */
+	.cs_density = 32,   /* full range so that get_mem_size() works, 32Gb per CS */
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,        /* Dynamic ODT, RZQ/2 */
+	.rtt_nom = 0,       /* Disabled */
+	.walat = 0,         /* Write additional latency */
+	.ralat = 5,         /* Read additional latency */
+	.mif3_mode = 3,     /* Command prediction working mode */
+	.bi_on = 1,         /* Bank interleaving enabled */
+	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+	.pd_fast_exit = 1,  /* enable precharge power-down fast exit */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,        /* Refresh cycles at 32KHz */
+	.refr = 3,          /* 4 refresh commands per refresh cycle */
+};
+
+static const struct mx6_mmdc_calibration mx6_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0009000E,
+	.p0_mpwldectrl1 = 0x0018000B,
+	.p1_mpwldectrl0 = 0x00060015,
+	.p1_mpwldectrl1 = 0x0006000E,
+	.p0_mpdgctrl0 = 0x432A0338,
+	.p0_mpdgctrl1 = 0x03260324,
+	.p1_mpdgctrl0 = 0x43340344,
+	.p1_mpdgctrl1 = 0x031E027C,
+	.p0_mprddlctl = 0x33272D2E,
+	.p1_mprddlctl = 0x2F312B37,
+	.p0_mpwrdlctl = 0x3A35433C,
+	.p1_mpwrdlctl = 0x4336453F,
+};
+
+static const struct mx6_ddr3_cfg ddr3_cfg = {
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1312,
+	.trcmin = 4812,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+struct mx6_ddr_sysinfo sysinfo_it = {
+	.dsize = 2,         /* width of data bus: 2=64 */
+	.cs_density = 32,   /* full range so that get_mem_size() works, 32Gb per CS */
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 1,        /* Dynamic ODT, RZQ/4 */
+	.rtt_nom = 1,       /* RZQ/4 */
+	.walat = 0,         /* Write additional latency */
+	.ralat = 5,         /* Read additional latency */
+	.mif3_mode = 3,     /* Command prediction working mode */
+	.bi_on = 1,         /* Bank interleaving enabled */
+	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+	.pd_fast_exit = 1,  /* enable precharge power-down fast exit */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,        /* Refresh cycles at 32KHz */
+	.refr = 7,          /* 8 refresh commands per refresh cycle */
+};
+
+static const struct mx6_mmdc_calibration mx6_mmdc_calib_it = {
+	.p0_mpwldectrl0 = 0x0009000E,
+	.p0_mpwldectrl1 = 0x0018000B,
+	.p1_mpwldectrl0 = 0x00060015,
+	.p1_mpwldectrl1 = 0x0006000E,
+	.p0_mpdgctrl0 = 0x03300338,
+	.p0_mpdgctrl1 = 0x03240324,
+	.p1_mpdgctrl0 = 0x03440350,
+	.p1_mpdgctrl1 = 0x032C0308,
+	.p0_mprddlctl = 0x40363C3E,
+	.p1_mprddlctl = 0x3C3E3C46,
+	.p0_mpwrdlctl = 0x403E463E,
+	.p1_mpwrdlctl = 0x4A384C46,
+};
+
+static const struct mx6_ddr3_cfg ddr3_cfg_it = {
+	.mem_speed = 1066,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1312,
+	.trcmin = 4812,
+	.trasmin = 3500,
+	.SRT = 1,
+};
+
 
 /* Perform DDR DRAM calibration */
-static void spl_dram_perform_cal(void)
+static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
 {
 #ifdef CONFIG_MX6_DDRCAL
 	int err;
-	struct mx6_ddr_sysinfo ddr_sysinfo = {
-		.dsize = 2,
-	};
 
-	err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+	err = mmdc_do_write_level_calibration(ddr_sysinfo);
 	if (err)
 		printf("error %d from write level calibration\n", err);
-	err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+	err = mmdc_do_dqs_calibration(ddr_sysinfo);
 	if (err)
 		printf("error %d from dqs calibration\n", err);
 #endif
@@ -1061,23 +985,35 @@ static void spl_dram_perform_cal(void)
 
 static void spl_dram_init(void)
 {
-	int minc, maxc;
+	bool temp_grade_it;
 
-	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	switch (get_cpu_temp_grade(NULL, NULL)) {
 	case TEMP_COMMERCIAL:
 	case TEMP_EXTCOMMERCIAL:
 		puts("Commercial temperature grade DDR3 timings.\n");
-		ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
+		temp_grade_it = false;
 		break;
 	case TEMP_INDUSTRIAL:
 	case TEMP_AUTOMOTIVE:
 	default:
 		puts("Industrial temperature grade DDR3 timings.\n");
-		ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
+		temp_grade_it = true;
 		break;
 	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+
+	if (temp_grade_it)
+		mx6_dram_cfg(&sysinfo_it, &mx6_mmdc_calib_it, &ddr3_cfg_it);
+	else
+		mx6_dram_cfg(&sysinfo, &mx6_mmdc_calib, &ddr3_cfg);
+
 	udelay(100);
-	spl_dram_perform_cal();
+
+	if (temp_grade_it)
+		spl_dram_perform_cal(&sysinfo_it);
+	else
+		spl_dram_perform_cal(&sysinfo);
 }
 
 void board_init_f(ulong dummy)

board/toradex/colibri_imx6/colibri_imx6.c

@@ -980,13 +980,17 @@ static void ccgr_init(void)
 /*
  * Setup CCM_CCOSR register as follows:
  *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
+ * clko2_en  = 1     --> CKO2 enabled
+ * clko2_div = 000   --> divide by 1
+ * clko2_sel = 01110 --> osc_clk (24MHz)
  *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ * clk_out_sel = 1   --> Output CKO2 to CKO1
+ *
+ * This sets both CLKO2/CLKO1 output to 24MHz,
+ * CLKO1 configuration not relevant because of clk_out_sel
+ * (CLKO1 set to default)
  */
-	writel(0x000000FB, &ccm->ccosr);
+	writel(0x010E0101, &ccm->ccosr);
 }
 
 static void ddr_init(int *table, int size)

boot/image-fit.c

@@ -1264,8 +1264,7 @@ int calculate_hash(const void *data, int data_len, const char *name,
 static int fit_image_check_hash(const void *fit, int noffset, const void *data,
 				size_t size, char **err_msgp)
 {
-	DEFINE_ALIGN_BUFFER(uint8_t, value, FIT_MAX_HASH_LEN,
-			    ARCH_DMA_MINALIGN);
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, value, FIT_MAX_HASH_LEN);
 	int value_len;
 	const char *algo;
 	uint8_t *fit_value;

cmd/i2c.c

@@ -200,10 +200,10 @@ void i2c_init_board(void)
  *
  * Returns the address length.
  */
-static uint get_alen(char *arg, int default_len)
+static uint get_alen(char *arg, uint default_len)
 {
-	int	j;
-	int	alen;
+	uint	j;
+	uint	alen;
 
 	alen = default_len;
 	for (j = 0; j < 8; j++) {
@@ -247,7 +247,7 @@ static int do_i2c_read(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	uint	chip;
 	uint	devaddr, length;
-	int alen;
+	uint	alen;
 	u_char  *memaddr;
 	int ret;
 #if CONFIG_IS_ENABLED(DM_I2C)
@@ -301,7 +301,7 @@ static int do_i2c_write(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	uint	chip;
 	uint	devaddr, length;
-	int alen;
+	uint	alen;
 	u_char  *memaddr;
 	int ret;
 #if CONFIG_IS_ENABLED(DM_I2C)
@@ -469,8 +469,8 @@ static int do_i2c_md(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	uint	chip;
 	uint	addr, length;
-	int alen;
-	int	j, nbytes, linebytes;
+	uint	alen;
+	uint	j, nbytes, linebytes;
 	int ret;
 #if CONFIG_IS_ENABLED(DM_I2C)
 	struct udevice *dev;
@@ -589,9 +589,9 @@ static int do_i2c_mw(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	uint	chip;
 	ulong	addr;
-	int	alen;
+	uint	alen;
 	uchar	byte;
-	int	count;
+	uint	count;
 	int ret;
 #if CONFIG_IS_ENABLED(DM_I2C)
 	struct udevice *dev;
@@ -676,8 +676,8 @@ static int do_i2c_crc(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	uint	chip;
 	ulong	addr;
-	int	alen;
-	int	count;
+	uint	alen;
+	uint	count;
 	uchar	byte;
 	ulong	crc;
 	ulong	err;
@@ -985,7 +985,7 @@ static int do_i2c_loop(struct cmd_tbl *cmdtp, int flag, int argc,
 		       char *const argv[])
 {
 	uint	chip;
-	int alen;
+	uint	alen;
 	uint	addr;
 	uint	length;
 	u_char	bytes[16];

configs/ae350_rv32_spl_defconfig

@@ -15,7 +15,6 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MMC=y
@@ -40,3 +39,4 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set

configs/ae350_rv32_spl_xip_defconfig

@@ -17,7 +17,6 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MMC=y
@@ -42,3 +41,4 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set

configs/ae350_rv64_spl_defconfig

@@ -16,7 +16,6 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MMC=y
@@ -41,3 +40,4 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set

configs/ae350_rv64_spl_xip_defconfig

@@ -18,7 +18,6 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_MMC=y
@@ -43,3 +42,4 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
+# CONFIG_BINMAN_FDT is not set

configs/imx8mm_data_modul_edm_sbc_defconfig

@@ -156,6 +156,7 @@ CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 # CONFIG_INPUT is not set
 CONFIG_MISC=y
+CONFIG_USB_HUB_USB251XB=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_SUPPORT_EMMC_BOOT=y

configs/imx8mn_bsh_smm_s2_defconfig

@@ -30,8 +30,10 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_DMA=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_PROMPT="> "
@@ -41,6 +43,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),1m(nanddtb),8m(nandtee),-(nandrootfs)"
+CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -65,6 +68,9 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y
 CONFIG_NAND_MXS=y
 CONFIG_NAND_MXS_DT=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xD8000
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x4058000
 CONFIG_PHYLIB=y
 CONFIG_PHY_NXP_TJA11XX=y
 CONFIG_DM_ETH=y

configs/imx8mn_evk_defconfig

@@ -46,9 +46,6 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y

configs/kontron-sl-mx8mm_defconfig

@@ -16,6 +16,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_KONTRON_MX8MM=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x42000000
@@ -99,6 +100,7 @@ CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_PCA9450=y
 CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_CONS_INDEX=2

configs/nanopi-r2s-rk3328_defconfig

@@ -45,6 +45,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
 CONFIG_TPL_OF_PLATDATA=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TPL_DM=y
 CONFIG_REGMAP=y

configs/pinebook-pro-rk3399_defconfig

@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00200000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
@@ -22,7 +23,6 @@ CONFIG_MISC_INIT_R=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
-CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y

configs/rockpro64-rk3399_defconfig

@@ -42,6 +42,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_SATA_SIL=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y

configs/socfpga_chameleonv3_defconfig

@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FPGA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_ATSHA204A=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y

disk/disk-uclass.c

@@ -8,6 +8,7 @@
 
 #define LOG_CATEGORY UCLASS_PARTITION
 
+#include <common.h>
 #include <blk.h>
 #include <dm.h>
 #include <log.h>

drivers/clk/altera/clk-mem-n5x.c

@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #include <common.h>

drivers/clk/altera/clk-mem-n5x.h

@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #ifndef	_CLK_MEM_N5X_

drivers/clk/altera/clk-n5x.c

@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #include <common.h>

drivers/clk/altera/clk-n5x.h

@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  */
 
 #ifndef	_CLK_N5X_

drivers/clk/sunxi/clk_sun6i_rtc.c

@@ -24,6 +24,8 @@ static const struct udevice_id sun6i_rtc_ids[] = {
 	{ .compatible = "allwinner,sun8i-v3-rtc" },
 	{ .compatible = "allwinner,sun50i-h5-rtc" },
 	{ .compatible = "allwinner,sun50i-h6-rtc" },
+	{ .compatible = "allwinner,sun50i-h616-rtc" },
+	{ .compatible = "allwinner,sun50i-r329-rtc" },
 	{ }
 };
 

drivers/fpga/socfpga_arria10.c

@@ -30,6 +30,14 @@
 #define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT	0x1000000
 #define DEFAULT_DDR_LOAD_ADDRESS	0x400
+#define DDR_BUFFER_SIZE		0x100000
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE	0x2000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -72,6 +80,13 @@ static int wait_for_user_mode(void)
 		1, FPGA_TIMEOUT_MSEC, false);
 }
 
+static int wait_for_fifo_empty(void)
+{
+	return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+		1, FPGA_TIMEOUT_MSEC, false);
+}
+
 int is_fpgamgr_early_user_mode(void)
 {
 	return (readl(&fpga_manager_base->imgcfg_stat) &
@@ -526,7 +541,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 #ifdef CONFIG_FS_LOADER
 static int first_loading_rbf_to_buffer(struct udevice *dev,
 				struct fpga_loadfs_info *fpga_loadfs,
-				u32 *buffer, size_t *buffer_bsize)
+				u32 *buffer, size_t *buffer_bsize,
+				size_t *buffer_bsize_ori)
 {
 	u32 *buffer_p = (u32 *)*buffer;
 	u32 *loadable = buffer_p;
@@ -674,6 +690,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
 		}
 
 		buffer_size = rbf_size;
+		*buffer_bsize_ori = DDR_BUFFER_SIZE;
 	}
 
 	debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +703,16 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
 	 * chunk by chunk transfer is required due to smaller buffer size
 	 * compare to bitstream
 	 */
+
+	if (buffer_size > MAX_FIRST_LOAD_SIZE)
+		buffer_size = MAX_FIRST_LOAD_SIZE;
+
 	if (rbf_size <= buffer_size) {
 		/* Loading whole bitstream into buffer */
 		buffer_size = rbf_size;
 		fpga_loadfs->remaining = 0;
 	} else {
+		buffer_size -= rbf_offset % buffer_size;
 		fpga_loadfs->remaining -= buffer_size;
 	}
 
@@ -806,7 +828,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 	 * function below.
 	 */
 	ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
-					   &buffer_sizebytes);
+					   &buffer_sizebytes,
+					   &buffer_sizebytes_ori);
 	if (ret == 1) {
 		printf("FPGA: Skipping configuration ...\n");
 		return 0;
@@ -858,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 
 		WATCHDOG_RESET();
 	}
+	wait_for_fifo_empty();
 
 	if (fpga_loadfs.rbfinfo.section == periph_section) {
 		if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {

drivers/gpio/Kconfig

@@ -365,6 +365,7 @@ config SANDBOX_GPIO_COUNT
 config SUNXI_GPIO
 	bool "Allwinner GPIO driver"
 	depends on ARCH_SUNXI
+	select SPL_STRTO if SPL
 	help
 	  Support the GPIO device in Allwinner SoCs.
 

drivers/misc/atsha204a-i2c.c

@@ -21,7 +21,8 @@
 #include <linux/bitrev.h>
 #include <u-boot/crc.h>
 
-#define ATSHA204A_TWLO			60
+#define ATSHA204A_TWLO_US		60
+#define ATSHA204A_TWHI_US		2500
 #define ATSHA204A_TRANSACTION_TIMEOUT	100000
 #define ATSHA204A_TRANSACTION_RETRY	5
 #define ATSHA204A_EXECTIME		5000
@@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev)
 			continue;
 		}
 
-		udelay(ATSHA204A_TWLO);
+		udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
 
 		res = atsha204a_recv_resp(dev, &resp);
 		if (res) {

drivers/mtd/nand/raw/mxs_nand_spl.c

@@ -29,7 +29,19 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
 
 	/* Serially input address */
 	if (column != -1) {
+		/* Adjust columns for 16 bit buswidth */
+		if (chip->options & NAND_BUSWIDTH_16 &&
+				!nand_opcode_8bits(command))
+			column >>= 1;
 		chip->cmd_ctrl(mtd, column, NAND_ALE);
+
+		/*
+		 * Assume LP NAND here, so use two bytes column address
+		 * but not for CMD_READID and CMD_PARAM, which require
+		 * only one byte column address
+		 */
+		if (command != NAND_CMD_READID &&
+			command != NAND_CMD_PARAM)
 			chip->cmd_ctrl(mtd, column >> 8, NAND_ALE);
 	}
 	if (page_addr != -1) {

drivers/nvme/nvme_apple.c

@@ -12,6 +12,7 @@
 
 #include <asm/io.h>
 #include <asm/arch/rtkit.h>
+#include <asm/arch/sart.h>
 #include <linux/iopoll.h>
 
 /* ASC registers */
@@ -66,6 +67,8 @@ struct apple_nvme_priv {
 	void *asc;		/* ASC registers */
 	struct reset_ctl_bulk resets; /* ASC reset */
 	struct mbox_chan chan;
+	struct apple_sart *sart;
+	struct apple_rtkit *rtk;
 	struct ans_nvmmu_tcb *tcbs[NVME_Q_NUM]; /* Submission queue TCBs */
 	u32 __iomem *q_db[NVME_Q_NUM]; /* Submission queue doorbell */
 };
@@ -143,11 +146,51 @@ static void apple_nvme_complete_cmd(struct nvme_queue *nvmeq,
 	nvmeq->sq_tail = tail;
 }
 
+static int nvme_shmem_setup(void *cookie, struct apple_rtkit_buffer *buf)
+{
+	struct apple_nvme_priv *priv = (struct apple_nvme_priv *)cookie;
+
+	if (!buf || buf->dva || !buf->size)
+		return -1;
+
+	buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K));
+	if (!buf->buffer)
+		return -ENOMEM;
+
+	if (!sart_add_allowed_region(priv->sart, buf->buffer, buf->size)) {
+		free(buf->buffer);
+		buf->buffer = NULL;
+		buf->size = 0;
+		return -1;
+	}
+
+	buf->dva = (u64)buf->buffer;
+
+	return 0;
+}
+
+static void nvme_shmem_destroy(void *cookie, struct apple_rtkit_buffer *buf)
+{
+	struct apple_nvme_priv *priv = (struct apple_nvme_priv *)cookie;
+
+	if (!buf)
+		return;
+
+	if (buf->buffer) {
+		sart_remove_allowed_region(priv->sart, buf->buffer, buf->size);
+		free(buf->buffer);
+		buf->buffer = NULL;
+		buf->size = 0;
+		buf->dva = 0;
+	}
+}
+
 static int apple_nvme_probe(struct udevice *dev)
 {
 	struct apple_nvme_priv *priv = dev_get_priv(dev);
 	fdt_addr_t addr;
-	u32 ctrl, stat;
+	ofnode of_sart;
+	u32 ctrl, stat, phandle;
 	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
@@ -167,12 +210,27 @@ static int apple_nvme_probe(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 
+	ret = dev_read_u32(dev, "apple,sart", &phandle);
+	if (ret < 0)
+		return ret;
+
+	of_sart = ofnode_get_by_phandle(phandle);
+	priv->sart = sart_init(of_sart);
+	if (!priv->sart)
+		return -EINVAL;
+
 	ctrl = readl(priv->asc + REG_CPU_CTRL);
 	writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
 
-	ret = apple_rtkit_init(&priv->chan);
-	if (ret < 0)
+	priv->rtk = apple_rtkit_init(&priv->chan, priv, nvme_shmem_setup, nvme_shmem_destroy);
+	if (!priv->rtk)
+		return -ENOMEM;
+
+	ret = apple_rtkit_boot(priv->rtk);
+	if (ret < 0) {
+		printf("%s: NVMe apple_rtkit_boot returned: %d\n", __func__, ret);
 		return ret;
+	}
 
 	ret = readl_poll_sleep_timeout(priv->base + ANS_BOOT_STATUS, stat,
 				       (stat == ANS_BOOT_STATUS_OK), 100,
@@ -206,11 +264,17 @@ static int apple_nvme_remove(struct udevice *dev)
 
 	nvme_shutdown(dev);
 
-	apple_rtkit_shutdown(&priv->chan, APPLE_RTKIT_PWR_STATE_SLEEP);
+	apple_rtkit_shutdown(priv->rtk, APPLE_RTKIT_PWR_STATE_SLEEP);
 
 	ctrl = readl(priv->asc + REG_CPU_CTRL);
 	writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
 
+	apple_rtkit_free(priv->rtk);
+	priv->rtk = NULL;
+
+	sart_free(priv->sart);
+	priv->sart = NULL;
+
 	reset_assert_bulk(&priv->resets);
 	reset_deassert_bulk(&priv->resets);
 

drivers/phy/allwinner/phy-sun4i-usb.c

@@ -125,9 +125,9 @@ struct sun4i_usb_phy_info {
 
 struct sun4i_usb_phy_plat {
 	void __iomem *pmu;
-	int gpio_vbus;
-	int gpio_vbus_det;
-	int gpio_id_det;
+	struct gpio_desc gpio_vbus;
+	struct gpio_desc gpio_vbus_det;
+	struct gpio_desc gpio_id_det;
 	struct clk clocks;
 	struct reset_ctl resets;
 	int id;
@@ -224,8 +224,8 @@ static int sun4i_usb_phy_power_on(struct phy *phy)
 		initial_usb_scan_delay = 0;
 	}
 
-	if (usb_phy->gpio_vbus >= 0)
-		gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
+	if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
+		dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
 
 	return 0;
 }
@@ -235,8 +235,8 @@ static int sun4i_usb_phy_power_off(struct phy *phy)
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 
-	if (usb_phy->gpio_vbus >= 0)
-		gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
+	if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
+		dm_gpio_set_value(&usb_phy->gpio_vbus, 0);
 
 	return 0;
 }
@@ -386,8 +386,8 @@ int sun4i_usb_phy_vbus_detect(struct phy *phy)
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 	int err = 1, retries = 3;
 
-	if (usb_phy->gpio_vbus_det >= 0) {
-		err = gpio_get_value(usb_phy->gpio_vbus_det);
+	if (dm_gpio_is_valid(&usb_phy->gpio_vbus_det)) {
+		err = dm_gpio_get_value(&usb_phy->gpio_vbus_det);
 		/*
 		 * Vbus may have been provided by the board and just turned off
 		 * some milliseconds ago on reset. What we're measuring then is
@@ -395,7 +395,7 @@ int sun4i_usb_phy_vbus_detect(struct phy *phy)
 		 */
 		while (err > 0 && retries--) {
 			mdelay(100);
-			err = gpio_get_value(usb_phy->gpio_vbus_det);
+			err = dm_gpio_get_value(&usb_phy->gpio_vbus_det);
 		}
 	} else if (data->vbus_power_supply) {
 		err = regulator_get_enable(data->vbus_power_supply);
@@ -409,10 +409,10 @@ int sun4i_usb_phy_id_detect(struct phy *phy)
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 
-	if (usb_phy->gpio_id_det < 0)
-		return usb_phy->gpio_id_det;
+	if (!dm_gpio_is_valid(&usb_phy->gpio_id_det))
+		return -1;
 
-	return gpio_get_value(usb_phy->gpio_id_det);
+	return dm_gpio_get_value(&usb_phy->gpio_id_det);
 }
 
 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
@@ -454,35 +454,42 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 		if (data->cfg->missing_phys & BIT(i))
 			continue;
 
-		phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
-		if (phy->gpio_vbus >= 0) {
-			ret = gpio_request(phy->gpio_vbus, "usb_vbus");
+		ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus);
+		if (ret == 0) {
+			ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus");
 			if (ret)
 				return ret;
-			ret = gpio_direction_output(phy->gpio_vbus, 0);
+			ret = dm_gpio_set_dir_flags(&phy->gpio_vbus,
+						    GPIOD_IS_OUT);
+			if (ret)
+				return ret;
+			ret = dm_gpio_set_value(&phy->gpio_vbus, 0);
 			if (ret)
 				return ret;
 		}
 
-		phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
-		if (phy->gpio_vbus_det >= 0) {
-			ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
+		ret = dm_gpio_lookup_name(info->gpio_vbus_det,
+					  &phy->gpio_vbus_det);
+		if (ret == 0) {
+			ret = dm_gpio_request(&phy->gpio_vbus_det,
+					      "usb_vbus_det");
 			if (ret)
 				return ret;
-			ret = gpio_direction_input(phy->gpio_vbus_det);
+			ret = dm_gpio_set_dir_flags(&phy->gpio_vbus_det,
+						    GPIOD_IS_IN);
 			if (ret)
 				return ret;
 		}
 
-		phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
-		if (phy->gpio_id_det >= 0) {
-			ret = gpio_request(phy->gpio_id_det, "usb_id_det");
+		ret = dm_gpio_lookup_name(info->gpio_id_det, &phy->gpio_id_det);
+		if (ret == 0) {
+			ret = dm_gpio_request(&phy->gpio_id_det, "usb_id_det");
 			if (ret)
 				return ret;
-			ret = gpio_direction_input(phy->gpio_id_det);
+			ret = dm_gpio_set_dir_flags(&phy->gpio_id_det,
+						GPIOD_IS_IN | GPIOD_PULL_UP);
 			if (ret)
 				return ret;
-			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 		}
 
 		if (data->cfg->dedicated_clocks)

drivers/power/pmic/pca9450.c

@@ -7,9 +7,12 @@
 #include <fdtdec.h>
 #include <errno.h>
 #include <dm.h>
+#include <dm/device_compat.h>
 #include <i2c.h>
+#include <linux/err.h>
 #include <log.h>
 #include <asm/global_data.h>
+#include <asm-generic/gpio.h>
 #include <power/pmic.h>
 #include <power/regulator.h>
 #include <power/pca9450.h>
@@ -26,6 +29,10 @@ static const struct pmic_child_info pmic_children_info[] = {
 	{ },
 };
 
+struct pca9450_priv {
+	struct gpio_desc *sd_vsel_gpio;
+};
+
 static int pca9450_reg_count(struct udevice *dev)
 {
 	return PCA9450_REG_NUM;
@@ -76,6 +83,24 @@ static int pca9450_bind(struct udevice *dev)
 	return 0;
 }
 
+static int pca9450_probe(struct udevice *dev)
+{
+	struct pca9450_priv *priv = dev_get_priv(dev);
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) {
+		priv->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel",
+							     GPIOD_IS_OUT |
+							     GPIOD_IS_OUT_ACTIVE);
+		if (IS_ERR(priv->sd_vsel_gpio)) {
+			ret = PTR_ERR(priv->sd_vsel_gpio);
+			dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret);
+		}
+	}
+
+	return ret;
+}
+
 static struct dm_pmic_ops pca9450_ops = {
 	.reg_count = pca9450_reg_count,
 	.read = pca9450_read,
@@ -94,5 +119,7 @@ U_BOOT_DRIVER(pmic_pca9450) = {
 	.id = UCLASS_PMIC,
 	.of_match = pca9450_ids,
 	.bind = pca9450_bind,
+	.probe = pca9450_probe,
 	.ops = &pca9450_ops,
+	.priv_auto = sizeof(struct pca9450_priv),
 };

drivers/power/pmic/rk8xx.c

@@ -6,10 +6,82 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/lists.h>
 #include <errno.h>
 #include <log.h>
 #include <power/rk8xx_pmic.h>
 #include <power/pmic.h>
+#include <sysreset.h>
+
+static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct rk8xx_priv *priv = dev_get_priv(dev->parent);
+
+	if (type != SYSRESET_POWER_OFF)
+		return -EPROTONOSUPPORT;
+
+	switch (priv->variant) {
+	case RK805_ID:
+	case RK808_ID:
+	case RK816_ID:
+	case RK818_ID:
+		pmic_clrsetbits(dev->parent, REG_DEVCTRL, 0, BIT(0));
+		break;
+	case RK809_ID:
+	case RK817_ID:
+		pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0,
+				BIT(0));
+		break;
+	default:
+		printf("Unknown PMIC RK%x: Cannot shutdown\n",
+		       priv->variant);
+		return -EPROTONOSUPPORT;
+	};
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk8xx_sysreset_ops = {
+	.request	= rk8xx_sysreset_request,
+};
+
+U_BOOT_DRIVER(rk8xx_sysreset) = {
+	.name		= "rk8xx_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.ops		= &rk8xx_sysreset_ops,
+};
+
+/* In the event of a plug-in and the appropriate option has been
+ * selected, we simply shutdown instead of continue the normal boot
+ * process. Please note the rk808 is not supported as it doesn't
+ * have the appropriate register.
+ */
+void rk8xx_off_for_plugin(struct udevice *dev)
+{
+	struct rk8xx_priv *priv = dev_get_priv(dev);
+
+	switch (priv->variant) {
+	case RK805_ID:
+	case RK816_ID:
+	case RK818_ID:
+		if (pmic_reg_read(dev, RK8XX_ON_SOURCE) & RK8XX_ON_PLUG_IN) {
+			printf("Power Off due to plug-in event\n");
+			pmic_clrsetbits(dev, REG_DEVCTRL, 0, BIT(0));
+		}
+		break;
+	case RK809_ID:
+	case RK817_ID:
+		if (pmic_reg_read(dev, RK817_ON_SOURCE) & RK8XX_ON_PLUG_IN) {
+			printf("Power Off due to plug-in event\n");
+			pmic_clrsetbits(dev, RK817_REG_SYS_CFG3, 0,
+					BIT(0));
+		}
+		break;
+	default:
+		printf("PMIC RK%x: Cannot read boot reason.\n",
+		       priv->variant);
+	}
+}
 
 static struct reg_data rk817_init_reg[] = {
 /* enable the under-voltage protection,
@@ -61,7 +133,7 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
 static int rk8xx_bind(struct udevice *dev)
 {
 	ofnode regulators_node;
-	int children;
+	int children, ret;
 
 	regulators_node = dev_read_subnode(dev, "regulators");
 	if (!ofnode_valid(regulators_node)) {
@@ -72,6 +144,14 @@ static int rk8xx_bind(struct udevice *dev)
 
 	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
 
+	if (CONFIG_IS_ENABLED(SYSRESET)) {
+		ret = device_bind_driver_to_node(dev, "rk8xx_sysreset",
+						 "rk8xx_sysreset",
+						 dev_ofnode(dev), NULL);
+		if (ret)
+			return ret;
+	}
+
 	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
 	if (!children)
 		debug("%s: %s - no child found\n", __func__, dev->name);
@@ -163,6 +243,8 @@ static int rk8xx_probe(struct udevice *dev)
 		       pmic_reg_read(dev, on_source),
 		       pmic_reg_read(dev, off_source));
 	printf("\n");
+	if (CONFIG_IS_ENABLED(ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
+		rk8xx_off_for_plugin(dev);
 
 	return 0;
 }

drivers/sysreset/sysreset_socfpga.c

@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
 {
 	struct socfpga_sysreset_data *data = dev_get_priv(dev);
 
-	data->rstmgr_base = dev_read_addr_ptr(dev);
+	data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
 	return 0;
 }
 

drivers/usb/gadget/Kconfig

@@ -61,6 +61,7 @@ config USB_GADGET_PRODUCT_NUM
 	hex "Product ID of the USB device"
 	default 0x1010 if ARCH_SUNXI
 	default 0x310a if ROCKCHIP_RK3036
+	default 0x300a if ROCKCHIP_RK3066
 	default 0x310c if ROCKCHIP_RK3128
 	default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288
 	default 0x330a if ROCKCHIP_RK3328