Prepare v2009.11.1

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,80 @@
+commit 580ca3c2b1d032534195cd0bfd89aa11e8c03bb3
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 21 11:37:31 2010 +0100
+
+    ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration
+
+    A newer CPLD version on the 405EX evaluation board requires a different
+    EBC controller setup for the CPLD register access. This patch adds a CPLD
+    version detection for Kilauea and code to reconfigure the EBC controller
+    (chip select 2) for the old CPLD if no new version is found.
+
+    Additionally the CPLD version is printed upon bootup:
+
+    Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Acked-by: Wolfgang Denk <wd@denx.de>
+    Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>
+
+commit eb20392ca986074c78ee4f241a8f2369777a8df3
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Sat Jan 23 01:35:24 2010 +0200
+
+    ppc4xx: Fix sending type 1 PCI transactions
+
+    The list of 4xx SoCs that should send type 1 PCI transactions
+    is not defined correctly. As a result PCI-PCI bridges and devices
+    behind them are not identified. The following 4xx variants should
+    send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 57ab8a129dd4121711540e2b976aff882998de51
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Tue Jan 19 21:19:06 2010 +0200
+
+    ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs
+
+    On platforms where SPD EEPROM and another EEPROM have adjacent
+    I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
+    element array, otherwise DDR2 setup code would fail with the
+    following error:
+
+    ERROR: Unknown DIMM detected in slot 1
+
+    However, fixing SPD_EEPROM_ADDRESS would result in another
+    error:
+
+    ERROR: DIMM's DDR1 and DDR2 type can not be mixed.
+
+    This happens because initdram() routine does not explicitly
+    initialize dimm_populated array. This patch fixes the problem.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 17ab3057bde25208af71326c0ff213d05eadb318
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Tue Jan 19 17:37:13 2010 +0200
+
+    ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT
+
+    Bootstrap options G and F are reported incorrectly (G instead
+    of F and vice versa). This patch fixes this.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a200a7c04d89853d2a1395b96d8ca5e3dd754551
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 15 23:20:54 2009 +0100
+
+    Update CHANGELOG; prepare Prepare v2009.11
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit f9476902b789b0481b9df49af88d6ca94fb16fa0
 Author: Peter Tyser <ptyser@xes-inc.com>
 Date:	Tue Dec 15 12:10:47 2009 -0600

Makefile

@@ -23,7 +23,7 @@
 
 VERSION = 2009
 PATCHLEVEL = 11
-SUBLEVEL =
+SUBLEVEL = 1
 EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)

board/amcc/kilauea/kilauea.c

@@ -39,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+static int board_cpld_version(void)
+{
+	u32 cpld;
+
+	cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+	if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+		/*
+		 * Magic not found -> "old" CPLD revision which needs
+		 * the "old" EBC configuration
+		 */
+		mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+		      EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+		      EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+		      EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+		      EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+		      EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+		      EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+		/*
+		 * Return 0 for "old" CPLD version
+		 */
+		return 0;
+	}
+
+	/*
+	 * Magic found -> "new" CPLD revision which needs no new
+	 * EBC configuration
+	 */
+	return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
+}
+
 /*
  * Board early initialization function
  */
@@ -208,6 +239,13 @@ int board_early_init_f (void)
 	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
 	mtsdr(SDR0_PFC1, val);
 
+	/*
+	 * The CPLD version detection has to be the first access to
+	 * the CPLD, so we need to make this access this early and
+	 * save the CPLD version for later.
+	 */
+	gd->board_type = board_cpld_version();
+
 	/*
 	 * Configure FPGA register with PCIe reset
 	 */
@@ -276,7 +314,7 @@ int checkboard (void)
 		puts(", serial# ");
 		puts(s);
 	}
-	putc('\n');
+	printf(" (CPLD rev. %ld)\n", gd->board_type);
 
 	return (0);
 }

cpu/ppc4xx/44x_spd_ddr2.c

@@ -426,7 +426,7 @@ phys_size_t initdram(int board_type)
 	unsigned char spd0[MAX_SPD_BYTES];
 	unsigned char spd1[MAX_SPD_BYTES];
 	unsigned char *dimm_spd[MAXDIMMS];
-	unsigned long dimm_populated[MAXDIMMS];
+	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 	unsigned long num_dimm_banks;		/* on board dimm banks */
 	unsigned long val;
 	ddr_cas_id_t selected_cas = DDR_CAS_5;	/* preset to silence compiler */

cpu/ppc4xx/cpu.c

@@ -196,7 +196,7 @@ static char *bootstrap_str[] = {
 	"I2C (Addr 0x54)",	/* A8 */
 	"I2C (Addr 0x52)",	/* A4 */
 };
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 #endif
 
 #if defined(CONFIG_460SX)

drivers/pci/pci_indirect.c

@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
 	return 0;                                                        \
 }
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+      defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
 indirect_##rw##_config_##size(struct pci_controller *hose,		 \

include/configs/kilauea.h

@@ -47,6 +47,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+#define CONFIG_BOARD_TYPES
 #define CONFIG_BOARD_EMAC_COUNT
 
 /*-----------------------------------------------------------------------
@@ -522,9 +523,22 @@
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
 #endif
 
-/* Memory Bank 2 (FPGA) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP           0x9400C800
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x18000)
+/* Memory Bank 2 (FPGA) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
+					 EBC_BXAP_FWT_ENCODE(6) |	\
+					 EBC_BXAP_BWT_ENCODE(1) |	\
+					 EBC_BXAP_BCE_DISABLE |		\
+					 EBC_BXAP_BCT_2TRANS |		\
+					 EBC_BXAP_CSN_ENCODE(0) |	\
+					 EBC_BXAP_OEN_ENCODE(0) |	\
+					 EBC_BXAP_WBN_ENCODE(3) |	\
+					 EBC_BXAP_WBF_ENCODE(1) |	\
+					 EBC_BXAP_TH_ENCODE(4) |	\
+					 EBC_BXAP_RE_DISABLED |		\
+					 EBC_BXAP_SOR_DELAYED |		\
+					 EBC_BXAP_BEM_WRITEONLY |	\
+					 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(CONFIG_SYS_FPGA_BASE | 0x18000)
 
 #define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
 
@@ -573,7 +587,7 @@
  * Some Kilauea stuff..., mainly fpga registers
  */
 #define CONFIG_SYS_FPGA_REG_BASE		CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_FPGA_FIFO_BASE		(in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
+#define CONFIG_SYS_FPGA_FIFO_BASE		(CONFIG_SYS_FPGA_BASE | (1 << 10))
 
 /* interrupt */
 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT	0x80000000
@@ -604,4 +618,8 @@
 #define CONFIG_SYS_FPGA_USER_LED0		0x00000200
 #define CONFIG_SYS_FPGA_USER_LED1		0x00000100
 
+#define CONFIG_SYS_FPGA_MAGIC_MASK		0xffff0000
+#define CONFIG_SYS_FPGA_MAGIC			0xabcd0000
+#define CONFIG_SYS_FPGA_VER_MASK		0x0000ff00
+
 #endif	/* __CONFIG_H */