On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.
Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The new is_serdes_configured covers a broader range of devices than the
PCI specific code. Use it instead as we convert away from the
is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
With the cpu include paths moved, the gitignore paths need updating.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Tom Rix <tom@bumblecow.com>
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now used by all PowerPC variants that currently have these
functions implemented.
The functions now use the proper IO-accessor functions to read/write the
values.
This code also supports two different bootcount versions:
a) Use 2 separate words (2 * 32bit) to store the bootcounter
b) Use only 1 word (2 * 16bit) to store the bootcounter
Version b) was already used by MPC5xxx.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
for 83xx parts
Cc: Michael Zaidman <michael.zaidman@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
AMD recently changed the licensing of the RAM sizing code to the
GPLv2 (or at your option any later version)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
If the board has a high precision mico-second timer, it maked sense to use
it instead of the on-chip one
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Add support for newer (up to 2.6.33) kernels
Add zboot command which takes the address of a bzImage as its first
argument and (optionally) the size of the bzImage as the second argument
(the second argument is needed for older kernels which do not include
the bzImage size in the header)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
It is possibly to setup x86 boards to use non-PC/AT configurations. For
example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals.
This function allows the board to set itself up for maximum PC/AT
compatibility just before booting the Linux kernel (the Linux kernel
'just works' if everything is PC/AT compliant)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Currently, the GDT is either located in FLASH or in the non-relocated
U-Boot image in RAM. Both of these locations are unsafe as those
locations can be erased during a U-Boot update. Move the GDT into the
highest available memory location and relocate U-Boot to just below it
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Add a parameter to the 32-bit entry to indicate if entry is from Real
Mode or not. If entry is from Real Mode, execute the destructive 'sizer'
routine to determine memory size as we are booting cold and running in
Flash. If not entering from Real Mode, we are executing a U-Boot image
from RAM and therefore the memory size is already known (and running
'sizer' will destroy the running image)
There are now two 32-bit entry points. The first is the 'in RAM' entry
point which exists at the start of the U-Boot binary image. As such,
you can load u-boot.bin in RAM and jump directly to the load address
without needing to calculate any offsets. The second entry point is
used by the real-to-protected mode switch
This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load
the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot
prompt
Hopefully a later patch will completely elliminate any dependency on
TEXT_BASE like a relocatable linux kernel (perfect world)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This patch allows the low-level assembler boot-strap to obtain the RAM
size without calling the destructive 'sizer' routine. This allows
boot-strapping from a U-Boot image loaded in RAM
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
There is an error in how the assembler version of the sc520 memory size
reporting code works. As a result, it will only ever report at most the
size of one bank of RAM
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Shamelessly steal the Linux x86 crash handling code and shove it into
U-Boot (cool - it fits). Be sure to include suitable attribution to
Linus
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This avoids a possible overwrite of the (end of) ramdisk by u-boot.
The unused memory region for ppc boot currently starts 1k below the
do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since
do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may
very well use more than 1k stack space.
Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
For code archeologists, this is a nice example of copy and paste history.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The QONG module can be downsized and delivered
with 128MB instead of 256MB. The patch adds
run time support for the two different memory
configurations.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Replace call to imx_get_mpllclk with imx_get_armclk
to show frequency of ARM core instead of mpll internal
bus in print_cpuinfo.
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Because of s5pc1xx gpio is same as s5p seires SoC,
move gpio functions to drvier/gpio/
and modify structure's name from s5pc1xx_ to s5p_.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Because of other s5p series SoC will use these serial functions,
modify function's name and structure's name.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
