For configurations with gmii2rgmii and external phy the DT nodes link
should be gem->gmii2rgmii->phy. But due to limitation in Linux driver
the DT is mentioned as gem->phy and gmii2rgmii->phy as shown in below DT.
ethernet@ff0c0000 {
compatible = "cdns,zynqmp-gem\0cdns,gem";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;
reg = <0x00 0xff0c0000 0x00 0x1000>;
clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0d 0x875>;
power-domains = <0x0c 0x1e>;
clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>;
phy-handle = <0x0e>;
phy-mode = "gmii";
xlnx,ptp-enet-clock = <0x00>;
local-mac-address = [ff ff ff ff ff ff];
phandle = <0x4d>;
mdio {
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x4e>;
ethernet-phy@1 {
reg = <0x01>;
rxc-skew-ps = <0x708>;
txc-skew-ps = <0x708>;
phandle = <0x0e>;
};
gmii_to_rgmii_0@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
phy-handle = <0x0e>;
reg = <0x08>;
phandle = <0x4f>;
};
};
};
Since same DT is used in Linux and U-Boot we need to workaround this
issue by using the gmii2rgmii node which points to phy and we should
ignore the gem pointing to phy directly.
Do this workaround by updating priv->phydev->node value with
priv->phy_of_node only if it is not valid node.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/641eb13425ffe80e0743f60cf90d0f940577b9e9.1642162085.git.michal.simek@xilinx.com
Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.
USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
Perform reset before core initialization.
Standard flow which close to 99% users are using getting all IPs out of
reset that there is no need to reset IP again. This is because of all low
level initialization is done in previous bootloader stage.
In SOM case these IPs are not touched by previous bootloader stage that's
why reset needs to be called before IP is accessed to make sure that it is
in correct state.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/5ae1c85b282d632bb62030f1f24a0065661b9153.1638804318.git.michal.simek@xilinx.com
Xilinx DTS files are using two way how to describe ethernet phy.
The first (already supported) has phy as subnode of gem node.
eth {
phy-handle = <&phy0>;
phy0: ethernet-phy@21 {
...
};
};
The second has mdio subnode (with mdio name) which has phy subnode. This
structure allow hadling MDIO reset signal (based on Linux mdio.yaml)
eth {
phy-handle = <&phy0>;
mdio {
phy0: ethernet-phy@21 {
...
};
};
};
This patch adds support for the second case where mdio subnode
is found driver will look at its parent to find out which gem is handling
MDIO bus.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/6748007f0b6db9554d7a4b52352dce23ca403f9d.1638798796.git.michal.simek@xilinx.com
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze using the
CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the
reset routines to branch to this location instead.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
- meson64_android: handle errors on boot and run fastboot on boot failure
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Merge tag 'u-boot-amlogic-20211119' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- pinctrl: Correct the driver GPIO declaration
- meson64_android: handle errors on boot and run fastboot on boot failure
This should use the provided U_BOOT_DRIVER() macro so that the driver gets
added to the appropriate linker list. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7c9dcfed50 ("pinctrl: meson: rework gx pmx function")
Reported-by: Tom Rini <trini@konsulko.com>
Tested-by: Tom Rini <trini@konsulko.com> on libretech-cc
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
%d was being used as the specifier for size_t, leading to a
compiler warning
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Without get_desc, the tpm command will not provide a
description of the device in 'tpm device' or 'tpm info'.
Due to the characteristics of the Atmel TPM it isn't
possible to determine certain attributes (e.g open/close
status) without using the TPM stack (compare Infineon
and ST TPM drivers), so just print out the chip model
and udevice name as the identifier.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
This driver was broken due to an empty offset byte being prepended
at the start of every transmission.
The hardware does not mimic an EEPROM device with registers so
an offset byte is not required.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
There are no users of this driver without DM_I2C
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
sdhci:
- Fix emmc mini case with missing firmware interface
zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable
firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location
spi:
- gqsi: Fix write issue at low frequencies
net:
- gem: Disable broadcasts
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Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.01-rc3
sdhci:
- Fix emmc mini case with missing firmware interface
zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable
firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location
spi:
- gqsi: Fix write issue at low frequencies
net:
- gem: Disable broadcasts
This ensures the USB_MUSB_PIO_ONLY config is set to an apppropriate
value from the changes enabling USB_MUSB_GADGET does.
Namely, USB_MUSB_PIO_ONLY default to =y on USB_MUSB_SUNXI being y.
Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
With CONFIG_SYSRESET_WATCHDOG=y the sandbox can use a watchdog based system
reset.
To make this work calling sandbox_wdt_expire_now() must lead to a reset.
With this change we can test the development suggested in
[PATCH 0/4] Improved sysreset/watchdog uclass integration
https://lists.denx.de/pipermail/u-boot/2021-August/458656.html
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The driver supports the ds1339 as well, which was probably intended by
the author but prevented by a typo. Fix the typo.
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
- device-tree sync-up with Linux for ls1028a
- fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc,
spintable code, configs, qspi node, pci
- enable EFI_SET_TIME support in sl28
- powerpc: Drop -mstring
Convert our SPI TPM driver and use the newly added API
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Add support for devices that expose a TPMv2 though MMIO.
Apart from those devices, we can use the driver in our QEMU setups and
test TPM related code which is difficult to achieve using the sandbox
driver (e.g test the EFI TCG2 protocol).
It's worth noting that a previous patch added TPMv2 TIS core functions,
which the current driver is consuming.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
There's a lot of code duplication in U-Boot right now. All the TPM TIS
compatible drivers we have at the moment have their own copy of a TIS
implementation.
So let's create a common layer which implements the core TIS functions.
Any driver added from now own, which is compatible with the TIS spec, will
only have to provide the underlying bus communication mechanisms.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
With the upcoming TPM2 API, some of the functions name are part of the new
header file. So switch conflicting internal function names and defines.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
With the upcoming TPM2 API, some of the functions name are part of the new
header file. So switch conflicting internal function names and defines.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
- Remove nWP GPIO hog
- Increase SF bus frequency to 50Mhz and enable SFDP
- Disable video output for DHSOM
- Disable EFI
- Enable DFU_MTD support
- Create include file for STM32 gpio driver private data
- Split board and SOC STM32MP15 configuration
- Device tree alignement with v5.15-rc6 for STM32MP15
- Add binman support for STM32MP15x
- Normalise newlines for stm32prog
- Update OTP shadow registers in SPL
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Merge tag 'u-boot-stm32-20211110' of https://source.denx.de/u-boot/custodians/u-boot-stm
- DHSOM update:
- Remove nWP GPIO hog
- Increase SF bus frequency to 50Mhz and enable SFDP
- Disable video output for DHSOM
- Disable EFI
- Enable DFU_MTD support
- Create include file for STM32 gpio driver private data
- Split board and SOC STM32MP15 configuration
- Device tree alignement with v5.15-rc6 for STM32MP15
- Add binman support for STM32MP15x
- Normalise newlines for stm32prog
- Update OTP shadow registers in SPL
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.
This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.
This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.
Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.
This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Header file mach/cpu.h already defines MBUS_PCI_MEM_SIZE macro which
defines size of MBUS_PCI_MEM_BASE window. So use global MBUS_PCI_MEM_SIZE
macro instead of locally defined PCIE_MEM_SIZE macro. Both macros have same
definition.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
The Sunxi boards only support a 16 second watchdog timeout. This is too
short to boot Linux. The UEFI specification requires 300 seconds as
default timeout.
Change the default for CONFIG_WATCHDOG_AUTOSTART for ARCH_SUNXI.
Fixes: b147bd3607 ("sunxi: Enable watchdog timer support by default")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
In the current code, it doesn't reset the cursors of LUT entry and
StreamID at the beginning of the fixup, so it can result in LUT entry
setup and msi-map mismatch and LUT entries and StreamID leaking
when reload and fixup the DTB.
This patch move the initialization of LUT entry and StreamID cursors
to the beginning of the fixup to resolve the issues.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Use moveconfig.py script to convert CONFIG_SYS_FMAN_FW_ADDR,
CONFIG_SYS_QE_FW_ADDR and CONFIG_SYS_QE_FMAN_FW_LENGTH to Kconfig and
move these entries to defconfigs.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add support for the proper dwc3 device tree binding support as specified
in the offical device tree spec.
Initially, add support for the LS1028A support. Other SoCs should be
easy to add by just adding the corresponding compatible string.
Unfortunately, the device trees of all other layerscape SoCs are not
converted and uses a wrong compatible string only known in u-boot.
To maintain backwards compatibility with current u-boot device trees,
add the generic "fsl,layerscape-dwc3" compatible string.
OTG mode is not supported yet. The dr_mode in the devicetree will either
have to be set to peripheral or host.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
[backport from linux commit d9612c2f0449e24983a8b689603210486a930c90]
Enable the undefined length INCR burst type and set INCRx.
Different platform may has the different burst size type.
In order to get best performance, we need to tune the burst
size to one special value, instead of the default value.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
[backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3]
Add adjust_frame_length_quirk for writing to fladj register
which adjusts (micro)frame length to value provided by
"snps,quirk-frame-length-adjustment" property thus avoiding
USB 2.0 devices to time-out over a longer run
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Both dr_mode and maximum-speed properties are usually optional. Drivers
will still try to fetch the properties nonetheless, which leads to error
messages, although they are no errors. Change pr_err() to pr_debug().
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The official bindind of the PCIe controller of the ls1028a has the
following compatible string:
compatible = "fsl,ls1028a-pcie";
Additionally, the resource names and count are different. Update the
driver to support this binding and change the entry in the ls1028a
device tree.
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
Change the ls1028a device tree and add this new compatible to the fsl
specific xhci driver, otherwise the generic dwc3 driver will be used
with the compatibles above.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The driver will look for a named resource "ecc-addr", but this isn't the
official binding. In fact, the official device tree binding
documentation doesn't mention any resource names at all. But it is safe
to assume that it's the linux ones we have to use if we want to be
compatible with the linux device tree. Thus rename "ecc-addr" to
"sata-ecc" and convert all the users in u-boot.
While at it, also rename "sata-base" to "ahci" although its not used at
all.
This change doesn't affect the SATA controller on the ZynqMP.
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-lpuart";
Add the missing compatible to the driver and update the device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The official devicetree bindings specifies spi-num-chipselects as the
name. Use it.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Add the missing compatible to the driver and update the device tree.
We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness
is determined by the little-endian property and not by the compatible
string itself. Further, we won't need and specific details on the DMA
configuration (which is different on the LS1021A). If it's ever needed,
we can later add the more specific "fsl,ls1028a-dspi" compatible to the
driver.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
