treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA

Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make
it compatible with Linux' naming.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
This commit is contained in:
Marek Behún 2022-04-07 00:33:03 +02:00 committed by Ramon Fried
parent 6706d7dcbe
commit ffb0f6f488
61 changed files with 105 additions and 105 deletions

View File

@ -471,7 +471,7 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:

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@ -583,7 +583,7 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
@ -733,7 +733,7 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:

View File

@ -89,7 +89,7 @@ int board_eth_init(struct bd_info *bis)
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, 0);
break;
case PHY_INTERFACE_MODE_NONE:
case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
@ -99,7 +99,7 @@ int board_eth_init(struct bd_info *bis)
break;
}
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA)
fm_info_set_mdio(i, NULL);
else
fm_info_set_mdio(i,

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@ -1232,7 +1232,7 @@ phy_interface_t ofnode_read_phy_mode(ofnode node)
mode = ofnode_read_string(node, "phy-connection-type");
if (!mode)
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++)
if (!strcmp(mode, phy_interface_strings[i]))
@ -1240,5 +1240,5 @@ phy_interface_t ofnode_read_phy_mode(ofnode node)
debug("%s: Invalid PHY interface '%s'\n", __func__, mode);
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -1265,7 +1265,7 @@ static int ag7xxx_eth_of_to_plat(struct udevice *dev)
return ret;
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;

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@ -678,7 +678,7 @@ static int altera_tse_of_to_plat(struct udevice *dev)
struct eth_pdata *pdata = dev_get_plat(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;

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@ -425,7 +425,7 @@ static int bcm6348_eth_probe(struct udevice *dev)
/* get phy mode */
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -ENODEV;
/* get phy */

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@ -696,7 +696,7 @@ static int bcmgenet_eth_of_to_plat(struct udevice *dev)
/* Get phy mode from DT */
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,

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@ -921,7 +921,7 @@ int designware_eth_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);

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@ -1682,7 +1682,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
interface = eqos->config->interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
if (interface == PHY_INTERFACE_MODE_NA) {
pr_err("Invalid PHY interface\n");
return -EINVAL;
}
@ -1743,7 +1743,7 @@ static int eqos_probe_resources_imx(struct udevice *dev)
interface = eqos->config->interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
if (interface == PHY_INTERFACE_MODE_NA) {
pr_err("Invalid PHY interface\n");
return -EINVAL;
}

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@ -1315,7 +1315,7 @@ static int fecmxc_of_to_plat(struct udevice *dev)
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
#ifdef CONFIG_DM_REGULATOR

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@ -55,7 +55,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
#endif
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
@ -112,7 +112,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
(port == FM1_DTSEC2) ||
(port == FM1_DTSEC3) ||
(port == FM1_DTSEC4))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
}
}
@ -131,8 +131,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -130,7 +130,7 @@ static int fm_port_to_index(enum fm_port port)
/*
* Determine if an interface is actually active based on HW config
* we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if
* we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NA if
* the interface is not active based on HW cfg of the SoC
*/
void fman_enet_init(void)
@ -141,7 +141,7 @@ void fman_enet_init(void)
phy_interface_t enet_if;
enet_if = fman_port_enet_if(fm_info[i].port);
if (enet_if != PHY_INTERFACE_MODE_NONE) {
if (enet_if != PHY_INTERFACE_MODE_NA) {
fm_info[i].enabled = 1;
fm_info[i].enet_if = enet_if;
} else {
@ -221,12 +221,12 @@ phy_interface_t fm_info_get_enet_if(enum fm_port port)
int i = fm_port_to_index(port);
if (i == -1)
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if (fm_info[i].enabled)
return fm_info[i].enet_if;
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
static void

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@ -54,13 +54,13 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
@ -107,5 +107,5 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
break;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -54,19 +54,19 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
@ -118,5 +118,5 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
break;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -46,7 +46,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
/* DTSEC1 can be SGMII, RGMII or RMII */
if (port == FM1_DTSEC1) {
@ -68,5 +68,5 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_RGMII;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -54,7 +54,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
@ -91,8 +91,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -50,7 +50,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
@ -82,8 +82,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -56,7 +56,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
@ -99,8 +99,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -39,7 +39,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
return PHY_INTERFACE_MODE_XGMII;
@ -83,5 +83,5 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
break;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -56,8 +56,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -47,7 +47,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
@ -85,8 +85,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -61,7 +61,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
@ -73,7 +73,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
((is_serdes_configured(XAUI_FM2_MAC9)) ||
@ -166,5 +166,5 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
break;
}
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -277,7 +277,7 @@ static void enetc_start_pcs(struct udevice *dev)
}
priv->if_type = dev_read_phy_mode(dev);
if (priv->if_type == PHY_INTERFACE_MODE_NONE) {
if (priv->if_type == PHY_INTERFACE_MODE_NA) {
enetc_dbg(dev,
"phy-mode property not found, defaulting to SGMII\n");
priv->if_type = PHY_INTERFACE_MODE_SGMII;

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@ -553,7 +553,7 @@ static int ftgmac100_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);

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@ -567,7 +567,7 @@ static int higmac_of_to_plat(struct udevice *dev)
priv->macif_ctrl = dev_remap_addr_index(dev, 1);
priv->phyintf = dev_read_phy_mode(dev);
if (priv->phyintf == PHY_INTERFACE_MODE_NONE)
if (priv->phyintf == PHY_INTERFACE_MODE_NA)
return -ENODEV;
phy_node = dev_read_subnode(dev, "phy");

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@ -1127,7 +1127,7 @@ static int ldpaa_eth_bind(struct udevice *dev)
int phy_mode = -1;
phy_mode = dev_read_phy_mode(dev);
if (phy_mode == PHY_INTERFACE_MODE_NONE) {
if (phy_mode == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}

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@ -16,7 +16,7 @@ struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
{
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
@ -26,10 +26,10 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
dpmac_info[dpmac_id].enabled = 0;
dpmac_info[dpmac_id].id = 0;
dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NA;
enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
if (enet_if != PHY_INTERFACE_MODE_NONE) {
if (enet_if != PHY_INTERFACE_MODE_NA) {
dpmac_info[dpmac_id].enabled = 1;
dpmac_info[dpmac_id].id = dpmac_id;
dpmac_info[dpmac_id].enet_if = enet_if;
@ -183,10 +183,10 @@ phy_interface_t wriop_get_enet_if(int dpmac_id)
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if (dpmac_info[i].enabled)
return dpmac_info[i].enet_if;
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}

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@ -50,7 +50,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
switch (lane_prtcl) {
case SGMII1:
@ -66,7 +66,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
return PHY_INTERFACE_MODE_QSGMII;
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)

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@ -62,7 +62,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
return PHY_INTERFACE_MODE_SGMII;
@ -76,7 +76,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
return PHY_INTERFACE_MODE_QSGMII;
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)

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@ -58,7 +58,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id))
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
return PHY_INTERFACE_MODE_SGMII;
@ -78,7 +78,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
return PHY_INTERFACE_MODE_CAUI4;
return PHY_INTERFACE_MODE_NONE;
return PHY_INTERFACE_MODE_NA;
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII

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@ -1363,7 +1363,7 @@ static int macb_eth_probe(struct udevice *dev)
int ret;
macb->phy_interface = dev_read_phy_mode(dev);
if (macb->phy_interface == PHY_INTERFACE_MODE_NONE)
if (macb->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
/* Read phyaddr from DT */

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@ -954,7 +954,7 @@ static int jr2_probe(struct udevice *dev)
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
PHY_INTERFACE_MODE_NONE);
PHY_INTERFACE_MODE_NA);
if (phy)
board_phy_config(phy);
}

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@ -685,7 +685,7 @@ static int luton_probe(struct udevice *dev)
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
PHY_INTERFACE_MODE_NONE);
PHY_INTERFACE_MODE_NA);
if (phy && i >= MAX_INT_PORT)
board_phy_config(phy);
}

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@ -608,7 +608,7 @@ static int ocelot_probe(struct udevice *dev)
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
PHY_INTERFACE_MODE_NONE);
PHY_INTERFACE_MODE_NA);
if (phy && external_bus(priv, i))
board_phy_config(phy);
}

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@ -561,7 +561,7 @@ static int serval_probe(struct udevice *dev)
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
PHY_INTERFACE_MODE_NONE);
PHY_INTERFACE_MODE_NA);
if (phy)
board_phy_config(phy);
}

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@ -482,7 +482,7 @@ static int servalt_probe(struct udevice *dev)
continue;
phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
PHY_INTERFACE_MODE_NONE);
PHY_INTERFACE_MODE_NA);
}
return 0;

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@ -596,7 +596,7 @@ static int mt7620_setup_gmac_mode(struct mt7620_eth_priv *priv, u32 gmac,
case PHY_INTERFACE_MODE_RGMII:
ge_mode = MT7620_SYSC_GE_RGMII;
break;
case PHY_INTERFACE_MODE_NONE:
case PHY_INTERFACE_MODE_NA:
if (gmac == 2)
ge_mode = MT7620_SYSC_GE_ESW_PHY;
else
@ -620,7 +620,7 @@ static void mt7620_gsw_setup_port(struct mt7620_eth_priv *priv, u32 port,
{
u32 pmcr;
if (port_cfg->mode == PHY_INTERFACE_MODE_NONE) {
if (port_cfg->mode == PHY_INTERFACE_MODE_NA) {
if (port == 5) {
gsw_write(priv, GSW_PMCR(port), FORCE_MODE);
return;
@ -666,7 +666,7 @@ static void mt7620_gsw_setup_phy_polling(struct mt7620_eth_priv *priv)
{
int phy_addr_st, phy_addr_end;
if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NONE)
if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NA)
priv->ephy_num = NUM_FE_PHYS;
else
priv->ephy_num = NUM_FE_PHYS - 1;
@ -1057,7 +1057,7 @@ static int mt7620_eth_parse_gsw_port(struct mt7620_eth_priv *priv, u32 idx,
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_RMII:
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_NONE:
case PHY_INTERFACE_MODE_NA:
break;
default:
dev_err(priv->dev, "mt7620_eth: unsupported phy-mode\n");
@ -1128,14 +1128,14 @@ static int mt7620_eth_parse_gsw_cfg(struct udevice *dev)
if (ret)
return ret;
} else {
priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NONE;
priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NA;
}
subnode = ofnode_find_subnode(dev_ofnode(dev), "port5");
if (ofnode_valid(subnode))
return mt7620_eth_parse_gsw_port(priv, 1, subnode);
priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NONE;
priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NA;
return 0;
}

View File

@ -1449,7 +1449,7 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
/* Interface mode is required */
pdata->phy_interface = dev_read_phy_mode(dev);
priv->phy_interface = pdata->phy_interface;
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) {
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
printf("error: phy-mode is not set\n");
return -EINVAL;
}

View File

@ -1005,7 +1005,7 @@ static int mvgbe_of_to_plat(struct udevice *dev)
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
dmvgbe->phy_interface = pdata->phy_interface;

View File

@ -1804,7 +1804,7 @@ static int mvneta_of_to_plat(struct udevice *dev)
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;

View File

@ -4820,7 +4820,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
}
port->phy_interface = dev_read_phy_mode(dev);
if (port->phy_interface == PHY_INTERFACE_MODE_NONE) {
if (port->phy_interface == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}

View File

@ -550,7 +550,7 @@ static int pic32_eth_probe(struct udevice *dev)
/* get phy mode */
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
/* get phy addr */

View File

@ -1137,7 +1137,7 @@ static int qe_uec_of_to_plat(struct udevice *dev)
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;

View File

@ -679,7 +679,7 @@ int ravb_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = 1000;

View File

@ -920,7 +920,7 @@ int sh_ether_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = 1000;

View File

@ -749,7 +749,7 @@ static int ave_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = 0;

View File

@ -1034,7 +1034,7 @@ static int netsec_of_to_plat(struct udevice *dev)
priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,

View File

@ -947,7 +947,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
pdata->phy_interface = dev_read_phy_mode(dev);
printf("phy interface%d\n", pdata->phy_interface);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
if (priv->variant == H3_EMAC) {

View File

@ -607,7 +607,7 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
dev_read_u32(dev, "reg", &priv->port_id);
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) {
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id);
return -EINVAL;
}

View File

@ -1345,7 +1345,7 @@ static int cpsw_eth_of_to_plat(struct udevice *dev)
}
pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;

View File

@ -728,7 +728,7 @@ static int ks2_eth_parse_slave_interface(int netcp, int slave,
priv->has_mdio = true;
} else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
priv->phy_if = ofnode_read_phy_mode(offset_to_ofnode(slave));
if (priv->phy_if == PHY_INTERFACE_MODE_NONE)
if (priv->phy_if == PHY_INTERFACE_MODE_NA)
priv->phy_if = PHY_INTERFACE_MODE_RGMII;
pdata->phy_interface = priv->phy_if;

View File

@ -894,7 +894,7 @@ int tsec_probe(struct udevice *dev)
priv->tbiaddr = tbiaddr;
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
pdata->phy_interface = tsec_get_interface(priv);
priv->interface = pdata->phy_interface;

View File

@ -850,7 +850,7 @@ static int axi_emac_of_to_plat(struct udevice *dev)
}
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,

View File

@ -859,7 +859,7 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
}
pdata->phy_interface = dev_read_phy_mode(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
priv->interface = pdata->phy_interface;

View File

@ -1239,7 +1239,7 @@ ofnode ofnode_get_phy_node(ofnode eth_node);
* returns the corresponding PHY interface type.
*
* @mac_node: ofnode containing the property
* Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NONE on
* Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on
* error
*/
phy_interface_t ofnode_read_phy_mode(ofnode mac_node);

View File

@ -764,7 +764,7 @@ ofnode dev_get_phy_node(const struct udevice *dev);
* returns the corresponding PHY interface type.
*
* @dev: device representing the MAC
* Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NONE on
* Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on
* error
*/
phy_interface_t dev_read_phy_mode(const struct udevice *dev);

View File

@ -72,7 +72,7 @@ enum fm_eth_type {
#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
.fm = idx, \
.phy_regs = (void *)pregs, \
.enet_if = PHY_INTERFACE_MODE_NONE, \
.enet_if = PHY_INTERFACE_MODE_NA, \
#ifdef CONFIG_SYS_FMAN_V3
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \

View File

@ -39,7 +39,7 @@ typedef enum {
PHY_INTERFACE_MODE_NCSI,
PHY_INTERFACE_MODE_10GBASER,
PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_NONE, /* Must be last */
PHY_INTERFACE_MODE_NA, /* Must be last */
PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
@ -71,7 +71,7 @@ static const char * const phy_interface_strings[] = {
[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
[PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
[PHY_INTERFACE_MODE_NONE] = "",
[PHY_INTERFACE_MODE_NA] = "",
};
/* Backplane modes:
@ -86,8 +86,8 @@ static const char * const backplane_mode_strings[] = {
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
if (i > PHY_INTERFACE_MODE_NONE)
i = PHY_INTERFACE_MODE_NONE;
if (i > PHY_INTERFACE_MODE_NA)
i = PHY_INTERFACE_MODE_NA;
return phy_interface_strings[i];
}

View File

@ -691,7 +691,7 @@ struct vsc9953_vcap {
.phyaddr = 0, \
.index = idx, \
.phy_regs = NULL, \
.enet_if = PHY_INTERFACE_MODE_NONE, \
.enet_if = PHY_INTERFACE_MODE_NA, \
.bus = NULL, \
.phydev = NULL, \
}

View File

@ -199,8 +199,8 @@ struct phy_device *dm_eth_phy_connect(struct udevice *ethdev)
}
interface = dev_read_phy_mode(ethdev);
if (interface == PHY_INTERFACE_MODE_NONE)
dev_dbg(ethdev, "can't find interface mode, default to NONE\n");
if (interface == PHY_INTERFACE_MODE_NA)
dev_dbg(ethdev, "can't find interface mode, default to NA\n");
phy = dm_eth_connect_phy_handle(ethdev, interface);