armv8: ls1012a: Add support of ls1012afrdm board
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Prabhakar Kushwaha
York Sun
parent
3b6e3898c2
commit
ff78aa2ba1
@ -714,6 +714,15 @@ config TARGET_LS1012ARDB
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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config TARGET_LS1012AFRDM
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bool "Support ls1012afrdm"
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select ARM64
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help
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Support for Freescale LS1012AFRDM platform.
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The LS1012A Freedom board (FRDM) is a high-performance
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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config TARGET_LS1021AQDS
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bool "Support ls1021aqds"
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select CPU_V7
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@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig"
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source "board/freescale/ls1043ardb/Kconfig"
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source "board/freescale/ls1012aqds/Kconfig"
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source "board/freescale/ls1012ardb/Kconfig"
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source "board/freescale/ls1012afrdm/Kconfig"
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source "board/freescale/mx23evk/Kconfig"
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source "board/freescale/mx25pdk/Kconfig"
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source "board/freescale/mx28evk/Kconfig"
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@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1043a-qds-lpuart.dtb \
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fsl-ls1043a-rdb.dtb \
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fsl-ls1012a-qds.dtb \
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fsl-ls1012a-rdb.dtb
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fsl-ls1012a-rdb.dtb \
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fsl-ls1012a-frdm.dtb
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dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
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16
arch/arm/dts/fsl-ls1012a-frdm.dts
Normal file
16
arch/arm/dts/fsl-ls1012a-frdm.dts
Normal file
@ -0,0 +1,16 @@
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/*
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* Device Tree file for Freescale Layerscape-1012A family SoC.
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*
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* Copyright 2016, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "fsl-ls1012a-frdm.dtsi"
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/ {
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chosen {
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stdout-path = &duart0;
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};
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};
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37
arch/arm/dts/fsl-ls1012a-frdm.dtsi
Normal file
37
arch/arm/dts/fsl-ls1012a-frdm.dtsi
Normal file
@ -0,0 +1,37 @@
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/*
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* Device Tree file for Freescale Layerscape-1012A family SoC.
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*
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* Copyright 2016, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/include/ "fsl-ls1012a.dtsi"
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/ {
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model = "LS1012A FREEDOM Board";
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aliases {
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spi0 = &qspi;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fl128s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&duart0 {
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status = "okay";
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};
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15
board/freescale/ls1012afrdm/Kconfig
Normal file
15
board/freescale/ls1012afrdm/Kconfig
Normal file
@ -0,0 +1,15 @@
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if TARGET_LS1012AFRDM
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config SYS_BOARD
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default "ls1012afrdm"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1012afrdm"
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endif
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6
board/freescale/ls1012afrdm/MAINTAINERS
Normal file
6
board/freescale/ls1012afrdm/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
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LS1012AFRDM BOARD
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M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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S: Maintained
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F: board/freescale/ls1012afrdm/
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F: include/configs/ls1012afrdm.h
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F: configs/ls1012afrdm_qspi_defconfig
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7
board/freescale/ls1012afrdm/Makefile
Normal file
7
board/freescale/ls1012afrdm/Makefile
Normal file
@ -0,0 +1,7 @@
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#
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# Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ls1012afrdm.o
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58
board/freescale/ls1012afrdm/README
Normal file
58
board/freescale/ls1012afrdm/README
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@ -0,0 +1,58 @@
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Overview
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--------
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QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
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platform, with a complete debugging environment. The LS1012AFRDM board
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supports the QorIQ LS1012A processor and is optimized to support the
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high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
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LS1012A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
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SoC overview.
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LS1012AFRDM board Overview
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-----------------------
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- SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
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- 2 SGMII 1G PHYs
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- DDR Controller
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- 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
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operating at 1.35 V
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- QSPI
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- Onboard 512 Mbit QSPI flash memory running at speed up
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to 108/54 MHz
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- One high-speed USB 2.0/3.0 port, one USB 2.0 port
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- USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
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Micro-AB connector.
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- USB 2.0 port is a debug port (CMSIS DAP) and is configured
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as a Micro-AB device.
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- I2C controller
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- One I2C bus with connectivity to Arduino headers
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- UART
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- UART (Console): UART1 (Without flow control) for console
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- ARM JTAG support
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- ARM Cortex® 10-pin JTAG connector for LS1012A
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- CMSIS DAP through K20 microcontroller
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- SAI Audio interface
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- One SAI port, SAI 2 with full duplex support
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- Clocks
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- 25 MHz crystal for LS1012A
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- 8 MHz Crystal for K20
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- 24 MHz for SC16IS740IPW SPI to Dual UART bridge
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- Power Supplies
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- 5 V input supply from USB
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- 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
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other board interfaces
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Booting Options
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---------------
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QSPI Flash 1
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QSPI flash map
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--------------
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Images | Size |QSPI Flash Address
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------------------------------------------
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RCW + PBI | 1MB | 0x4000_0000
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U-boot | 1MB | 0x4010_0000
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U-boot Env | 1MB | 0x4020_0000
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PPA FIT image | 2MB | 0x4050_0000
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Linux ITB | ~53MB | 0x40A0_0000
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192
board/freescale/ls1012afrdm/ls1012afrdm.c
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192
board/freescale/ls1012afrdm/ls1012afrdm.c
Normal file
@ -0,0 +1,192 @@
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <fsl_csu.h>
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#include <environment.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
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{
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int timeout = 1000;
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out_be32(ptr, value);
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while (in_be32(ptr) & bits) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0)
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puts("Error: wait for clear timeout.\n");
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}
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int checkboard(void)
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{
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puts("Board: LS1012AFRDM ");
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return 0;
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}
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void mmdc_init(void)
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{
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struct mmdc_p_regs *mmdc =
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(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
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/* configure timing parms */
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out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
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out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
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out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
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out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
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/* other parms */
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out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
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out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
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out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
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out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
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/* out of reset delays */
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out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
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/* physical parms */
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
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out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
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/* Enable MMDC */
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
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/* dram init sequence: update MRs */
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
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CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
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/* dram init sequence: ZQCL */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
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CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
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FORCE_ZQ_AUTO_CALIBRATION);
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/* Calibrations now: wr lvl */
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
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CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
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set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
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mdelay(1);
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
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mdelay(1);
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/* Calibrations now: Read DQS gating calibration */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
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out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
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set_wait_for_bits_clear(&mmdc->mpdgctrl0,
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AUTO_RD_DQS_GATING_CALIBRATION_EN,
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AUTO_RD_DQS_GATING_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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/* Calibrations now: Read calibration */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
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set_wait_for_bits_clear(&mmdc->mprddlhwctl,
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AUTO_RD_CALIBRATION_EN,
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AUTO_RD_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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/* PD, SR */
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out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
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out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
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/* refresh scheme */
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set_wait_for_bits_clear(&mmdc->mdref,
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CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
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START_REFRESH);
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/* disable CON_REQ */
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out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
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}
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int dram_init(void)
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{
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mmdc_init();
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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29
configs/ls1012afrdm_qspi_defconfig
Normal file
29
configs/ls1012afrdm_qspi_defconfig
Normal file
@ -0,0 +1,29 @@
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CONFIG_ARM=y
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CONFIG_TARGET_LS1012AFRDM=y
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_SPI_FLASH=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_NETDEVICES=y
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CONFIG_SYS_NS16550=y
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44
include/configs/ls1012afrdm.h
Normal file
44
include/configs/ls1012afrdm.h
Normal file
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __LS1012ARDB_H__
|
||||
#define __LS1012ARDB_H__
|
||||
|
||||
#include "ls1012a_common.h"
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
|
||||
|
||||
#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000
|
||||
#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000
|
||||
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_XHCI_DWC3
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
#endif /* __LS1012ARDB_H__ */
|
||||
Loading…
Reference in New Issue
Block a user