Xilinx fixes for v2018.05-rc3

- Fix nand initialization
 - Runtime ddr detection for static DDR setting
 - Enable rewriting env locations
 - Sync defconfig for zc770 xm011
 - Remove useless ioremap in watchdog
 - Check return value from soc_clk_dump()
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Merge tag 'xilinx-for-v2018.05-rc3' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.05-rc3

- Fix nand initialization
- Runtime ddr detection for static DDR setting
- Enable rewriting env locations
- Sync defconfig for zc770 xm011
- Remove useless ioremap in watchdog
- Check return value from soc_clk_dump()
This commit is contained in:
Tom Rini 2018-04-23 10:50:38 -04:00
commit ff719a73d9
9 changed files with 24 additions and 25 deletions
arch/arm/mach-zynq
Kconfig
include/mach
board/xilinx
zynq
zynqmp
cmd
configs
drivers
mtd/nand
watchdog
include/configs

View File

@ -36,6 +36,7 @@ config ZYNQ_DDRC_INIT
want to skip ddr init and this option is useful for it.
config SYS_BOARD
string "Board name"
default "zynq"
config SYS_VENDOR

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@ -1,9 +0,0 @@
/*
* Copyright (C) 2017 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <nand.h>
void zynq_nand_init(void);

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@ -184,7 +184,8 @@ int dram_init(void)
#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
zynq_ddrc_init();

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@ -377,7 +377,8 @@ int dram_init(void)
#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}

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@ -16,7 +16,15 @@ int __weak soc_clk_dump(void)
static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
return soc_clk_dump();
int ret;
ret = soc_clk_dump();
if (ret < 0) {
printf("Clock dump error %d\n", ret);
ret = CMD_RET_FAILURE;
}
return ret;
}
static cmd_tbl_t cmd_clk_sub[] = {

View File

@ -29,11 +29,11 @@ CONFIG_CMD_CACHE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_DM_MMC=y
CONFIG_NAND=y
CONFIG_NAND_ZYNQ=y
CONFIG_DEBUG_UART_ZYNQ=y

View File

@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd)
return 0;
}
int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
{
struct zynq_nand_info *xnand;
struct mtd_info *mtd;
@ -1025,7 +1025,7 @@ int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
}
xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
mtd = get_nand_dev_by_index(0);
mtd = nand_to_mtd(nand_chip);
nand_chip->priv = xnand;
mtd->priv = nand_chip;
@ -1192,14 +1192,12 @@ fail:
return err;
}
#ifdef CONFIG_SYS_NAND_SELF_INIT
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
void __weak board_nand_init(void)
void board_nand_init(void)
{
struct nand_chip *nand = &nand_chip[0];
if (zynq_nand_init(nand, 0))
puts("ZYNQ NAND init failed\n");
}
#endif

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@ -25,7 +25,6 @@ struct cdns_regs {
struct cdns_wdt_priv {
bool rst;
u32 timeout;
void __iomem *reg;
struct cdns_regs *regs;
};
@ -224,12 +223,8 @@ static int cdns_wdt_stop(struct udevice *dev)
*/
static int cdns_wdt_probe(struct udevice *dev)
{
struct cdns_wdt_priv *priv = dev_get_priv(dev);
debug("%s: Probing wdt%u\n", __func__, dev->seq);
priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs));
cdns_wdt_stop(dev);
return 0;

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@ -127,7 +127,9 @@
#endif
/* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE (128 << 10)
#ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE (128 << 10)
#endif
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@ -135,7 +137,9 @@
/* Environment */
#ifndef CONFIG_ENV_IS_NOWHERE
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# define CONFIG_ENV_OFFSET 0xE0000
# ifndef CONFIG_ENV_OFFSET
# define CONFIG_ENV_OFFSET 0xE0000
# endif
#endif
/* enable preboot to be loaded before CONFIG_BOOTDELAY */