powerpc: P1020MBG: Separate from P1_P2_RDB_PC in Kconfig

Use TARGET_P1020MBG instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and other macros.

Remove macro CONFIG_P1020MBG.

Signed-off-by: York Sun <york.sun@nxp.com>

board/freescale/p1_p2_rdb_pc/Kconfig

@@ -1,4 +1,5 @@
-if TARGET_P1_P2_RDB_PC
+if TARGET_P1_P2_RDB_PC || \
+	TARGET_P1020MBG
 
 config SYS_BOARD
 	default "p1_p2_rdb_pc"

board/freescale/p1_p2_rdb_pc/ddr.c

@@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 30000,
 };
-#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 2,

board/freescale/p1_p2_rdb_pc/tlb.c

@@ -85,13 +85,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
-#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD)
 	/* 2G DDR on P1020MBG, map the second 1G */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* P1020MBG */
+#endif /* TARGET_P1020MBG */
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR