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ppc4xx: Enable booting with Option E on 460EX/EXr/GT

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This patch enables booting with option E on the PPC460EX/EXr/GT.
When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0.
The Software Boot Configuration Procedure is needed to engage the
PLL and perform a chip reset.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-05-19 11:13:24 +02:00
parent 39ddd10b04
commit fe7cca715c
2 changed files with 48 additions and 12 deletions
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53
arch/powerpc/cpu/ppc4xx/cpu_init.c
View File

@ -36,6 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_PLL_RECONFIG 0
#endif
#if defined(CONFIG_440EPX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
static void reset_with_rli(void)
{
u32 reg;
/*
* Set reload inhibit so configuration will persist across
* processor resets
*/
mfcpr(CPR0_ICFG, reg);
reg |= CPR0_ICFG_RLI_MASK;
mtcpr(CPR0_ICFG, reg);
/* Reset processor if configuration changed */
__asm__ __volatile__ ("sync; isync");
mtspr(SPRN_DBCR0, 0x20000000);
}
#endif
void reconfigure_pll(u32 new_cpu_freq)
{
#if defined(CONFIG_440EPX)
@ -166,19 +186,28 @@ void reconfigure_pll(u32 new_cpu_freq)
}
}
if (reset_needed) {
/*
* Set reload inhibit so configuration will persist across
* processor resets
*/
mfcpr(CPR0_ICFG, reg);
reg &= ~CPR0_ICFG_RLI_MASK;
reg |= 1 << 31;
mtcpr(CPR0_ICFG, reg);
/* Now reset the CPU if needed */
if (reset_needed)
reset_with_rli();
#endif
/* Reset processor if configuration changed */
__asm__ __volatile__ ("sync; isync");
mtspr(SPRN_DBCR0, 0x20000000);
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
u32 reg;
/*
* See "9.2.1.1 Booting with Option E" in the 460EX/GT
* users manual
*/
mfcpr(CPR0_PLLC, reg);
if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
/*
* Set engage bit
*/
reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
mtcpr(CPR0_PLLC, reg);
/* Now reset the CPU */
reset_with_rli();
}
#endif
}

7
include/ppc440.h
View File

@ -1719,6 +1719,13 @@
#define CPR0_PERD_PERDV0_MASK 0x07000000
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define CPR0_ICFG_RLI_MASK 0x80000000
#define CPR0_PLLC_RST 0x80000000
#define CPR0_PLLC_ENG 0x40000000
#endif
/*-----------------------------------------------------------------------------
| PCI Internal Registers et. al. (accessed via plb)
+----------------------------------------------------------------------------*/