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x86: ivybridge: Move more init to the probe() function

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Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-01-17 16:11:12 -07:00 committed by Bin Meng
parent 788cd90864
commit fe40bd4d8f
2 changed files with 43 additions and 43 deletions
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43
arch/x86/cpu/ivybridge/cpu.c
View File

@ -30,26 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
{
/* Enable port 80 POST on LPC */
pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
clrbits_le32(RCB_REG(GCS), 4);
}
/*
* Enable Prefetching and Caching.
*/
static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
{
u8 reg8;
pci_hose_read_config_byte(hose, dev, 0xdc, &reg8);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
}
static int set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
@ -99,22 +79,6 @@ static int set_flex_ratio_to_tdp_nominal(void)
return -EINVAL;
}
static void set_spi_speed(void)
{
u32 fdod;
/* Observe SPI Descriptor Component Section 0 */
writel(0x1000, RCB_REG(SPI_DESC_COMP0));
/* Extract the1 Write/Erase SPI Frequency from descriptor */
fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
fdod >>= 24;
fdod &= 7;
/* Set Software Sequence frequency to match */
clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
}
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
@ -143,13 +107,6 @@ int arch_cpu_init_dm(void)
if (!dev)
return -ENODEV;
enable_spi_prefetch(hose, PCH_LPC_DEV);
/* This is already done in start.S, but let's do it in C */
enable_port80_on_lpc(hose, PCH_LPC_DEV);
set_spi_speed();
/*
* We should do as little as possible before the serial console is
* up. Perhaps this should move to later. Our next lot of init

43
arch/x86/cpu/ivybridge/lpc.c
View File

@ -454,6 +454,42 @@ static void pch_fixups(pci_dev_t dev)
setbits_le32(RCB_REG(0x21a8), 0x3);
}
/*
* Enable Prefetching and Caching.
*/
static void enable_spi_prefetch(struct udevice *pch)
{
u8 reg8;
dm_pci_read_config8(pch, 0xdc, &reg8);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
dm_pci_write_config8(pch, 0xdc, reg8);
}
static void enable_port80_on_lpc(struct udevice *pch)
{
/* Enable port 80 POST on LPC */
dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
clrbits_le32(RCB_REG(GCS), 4);
}
static void set_spi_speed(void)
{
u32 fdod;
/* Observe SPI Descriptor Component Section 0 */
writel(0x1000, RCB_REG(SPI_DESC_COMP0));
/* Extract the1 Write/Erase SPI Frequency from descriptor */
fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
fdod >>= 24;
fdod &= 7;
/* Set Software Sequence frequency to match */
clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
}
/**
* lpc_early_init() - set up LPC serial ports and other early things
*
@ -492,6 +528,13 @@ static int lpc_early_init(struct udevice *dev)
dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
}
enable_spi_prefetch(dev->parent);
/* This is already done in start.S, but let's do it in C */
enable_port80_on_lpc(dev->parent);
set_spi_speed();
return 0;
}