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imx: support for conga-QMX8 board

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Add i.MX8QM qmx8 congatec board support

U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200)

CPU:   NXP i.MX8QM RevB A53 at 1200 MHz

Model: Congatec QMX8 Qseven series
Board: conga-QMX8
Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9
Boot:  SD2
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
switch to partitions #0, OK
mmc2 is current device
Net:
Error: ethernet@5b040000 address not set.
No ethernet found.

Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
This commit is contained in:
Oliver Graute
2021-05-31 15:50:40 +02:00
committed by Stefano Babic
parent 6ac4d44806
commit fe133eb192
17 changed files with 1469 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
board/congatec/cgtqmx8/Kconfig Normal file
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if TARGET_CONGA_QMX8
config SYS_BOARD
default "cgtqmx8"
config SYS_VENDOR
default "congatec"
config SYS_CONFIG_NAME
default "cgtqmx8"
source "board/congatec/common/Kconfig"
endif

7
board/congatec/cgtqmx8/MAINTAINERS Normal file
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i.MX8QM CGTQMX8 BOARD
M: Oliver Graute <oliver.graute@kococonnector.com>
S: Maintained
F: board/congatec/cgtqmx8/
F: arch/arm/dts/imx8qm-cgtqmx8.dts
F: include/configs/cgtqmx8.h
F: configs/cgtqmx8_defconfig

11
board/congatec/cgtqmx8/Makefile Normal file
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#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cgtqmx8.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif

460
board/congatec/cgtqmx8/cgtqmx8.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 congatec AG
* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
*/
#include <common.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <fsl_esdhc.h>
#include <init.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <usb.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
#include <power-domain.h>
DECLARE_GLOBAL_DATA_PTR;
#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
void board_late_mmc_env_init(void);
void init_clk_usdhc(u32 index);
int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
static void setup_iomux_uart(void)
{
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
}
int board_early_init_f(void)
{
/* sc_ipc_t ipcHndl = 0; */
sc_err_t scierr = 0;
/* When start u-boot in XEN VM, directly return */
/* if (IS_ENABLED(CONFIG_XEN)) */
/* return 0; */
/* ipcHndl = gd->arch.ipc_channel_handle; */
/* Power up UART0, this is very early while power domain is not working */
scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
if (scierr != SC_ERR_NONE)
return 0;
/* Set UART0 clock root to 80 MHz */
sc_pm_clock_rate_t rate = 80000000;
scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
if (scierr != SC_ERR_NONE)
return 0;
/* Enable UART0 clock root */
scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
if (scierr != SC_ERR_NONE)
return 0;
setup_iomux_uart();
return 0;
}
#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX)
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
};
static iomux_cfg_t emmc0[] = {
SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
static iomux_cfg_t usdhc1_sd[] = {
SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
static iomux_cfg_t usdhc2_sd[] = {
SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
struct power_domain pd;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 (onboard eMMC) USDHC1
* mmc1 (external SD card) USDHC2
* mmc2 (onboard µSD) USDHC3
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
/* onboard eMMC */
if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd))
power_domain_on(&pd);
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
init_clk_usdhc(0);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
/* external SD card */
if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd))
power_domain_on(&pd);
imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
init_clk_usdhc(1);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gpio_request(USDHC1_CD_GPIO, "sd1_cd");
gpio_direction_input(USDHC1_CD_GPIO);
break;
case 2:
/* onboard µSD */
if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd))
power_domain_on(&pd);
imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
init_clk_usdhc(2);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
gpio_request(USDHC2_CD_GPIO, "sd2_cd");
gpio_direction_input(USDHC2_CD_GPIO);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
}
return ret;
}
#endif /* CONFIG_FSL_ESDHC_IMX */
#if (IS_ENABLED(CONFIG_FEC_MXC))
#include <miiphy.h>
static iomux_cfg_t pad_enet0[] = {
SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
}
static void enet_device_phy_reset(void)
{
gpio_set_value(FEC0_RESET, 0);
udelay(50);
gpio_set_value(FEC0_RESET, 1);
/* The board has a long delay for this reset to become stable */
mdelay(200);
}
int board_eth_init(struct bd_info *bis)
{
setup_iomux_fec();
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
static int setup_fec(void)
{
/* Reset ENET PHY */
enet_device_phy_reset();
return 0;
}
#endif
#ifdef CONFIG_MXC_GPIO
#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
#define BKL_ENABLE IMX_GPIO_NR(1, 7)
static iomux_cfg_t board_gpios[] = {
SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
static void board_gpio_init(void)
{
imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
/* enable LVDS */
gpio_request(LVDS_ENABLE, "lvds_enable");
gpio_direction_output(LVDS_ENABLE, 1);
/* enable backlight */
gpio_request(BKL_ENABLE, "bkl_enable");
gpio_direction_output(BKL_ENABLE, 1);
/* ethernet reset */
gpio_request(FEC0_RESET, "enet0_reset");
gpio_direction_output(FEC0_RESET, 1);
}
#endif
int checkboard(void)
{
puts("Board: conga-QMX8\n");
build_info();
print_bootinfo();
return 0;
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_XEN))
return 0;
#ifdef CONFIG_MXC_GPIO
board_gpio_init();
#endif
#if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
#endif
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
/* TODO */
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
return 0;
}
#endif
int board_mmc_get_env_dev(int devno)
{
/* Use EMMC */
if (IS_ENABLED(CONFIG_XEN))
return 0;
return devno;
}
int mmc_map_to_kernel_blk(int dev_no)
{
/* Use EMMC */
if (IS_ENABLED(CONFIG_XEN))
return 0;
return dev_no;
}
extern u32 _end_ofs;
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "QMX8");
env_set("board_rev", "iMX8QM");
#endif
env_set("sec_boot", "no");
#ifdef CONFIG_AHAB_BOOT
env_set("sec_boot", "yes");
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
#ifdef IMX_LOAD_HDMI_FIMRWARE
char *end_of_uboot;
char command[256];
end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs
+ fdt_totalsize(gd->fdt_blob));
end_of_uboot += 9;
/* load hdmitxfw.bin and hdmirxfw.bin*/
memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
run_command(command, 0);
sprintf(command, "hdprx load 0x%x",
IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
run_command(command, 0);
#endif
return 0;
}
#ifdef CONFIG_FSL_FASTBOOT
#ifdef CONFIG_ANDROID_RECOVERY
int is_recovery_key_pressing(void)
{
return 0; /*TODO*/
}
#endif /*CONFIG_ANDROID_RECOVERY*/
#endif /*CONFIG_FSL_FASTBOOT*/
/* Only Enable USB3 resources currently */
int board_usb_init(int index, enum usb_init_type init)
{
return 0;
}

21
board/congatec/cgtqmx8/imximage.cfg Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */
APPEND mx8qm-ahab-container.img
/* Create the 2nd container */
CONTAINER
/* Add scfw image with exec attribute */
IMAGE SCU mx8qm-val-scfw-tcm.bin
/* Add ATF image with exec attribute */
IMAGE A35 bl31.bin 0x80000000
/* Add U-Boot image with load attribute */
DATA A35 u-boot-dtb.bin 0x80020000

77
board/congatec/cgtqmx8/spl.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
struct udevice *dev;
int offset;
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
while (offset != -FDT_ERR_NOTFOUND) {
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
NULL, true);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
"nxp,imx8-pd");
}
uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
puts("Normal Boot\n");
}
#if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}

48
board/congatec/common/Kconfig Normal file
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if !ARCH_IMX8M && !ARCH_IMX8
config CHAIN_OF_TRUST
depends on !FIT_SIGNATURE && SECURE_BOOT
imply CMD_BLOB
imply CMD_HASH if ARM
select FSL_CAAM
select SPL_BOARD_INIT if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
bool
default y
config CMD_ESBC_VALIDATE
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
default y if CHAIN_OF_TRUST
help
This option enables two commands used for secure booting:
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
endif
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
default n
help
This option enables LTC3882 voltage monitor read
functionality. It is used by common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
default n
help
This option enables LTC3882 voltage monitor set
functionality. It is used by common VID driver.
config USB_TCPC
bool "USB Typec port controller simple driver"
default n
help
Enable USB type-c port controller (TCPC) driver

23
board/congatec/common/Makefile Normal file
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#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
# necessary to create built-in.o
obj- := __dummy__.o
else
obj-y += mmc.o
endif

49
board/congatec/common/mmc.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
*/
#include <common.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <env.h>
#include <command.h>
#include <stdbool.h>
#include <mmc.h>
static int check_mmc_autodetect(void)
{
char *autodetect_str = env_get("mmcautodetect");
if ((autodetect_str) && (strcmp(autodetect_str, "yes") == 0))
return 1;
return 0;
}
/* This should be defined for each board */
__weak int mmc_map_to_kernel_blk(int dev_no)
{
return dev_no;
}
void board_late_mmc_env_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
if (!check_mmc_autodetect())
return;
env_set_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
mmc_map_to_kernel_blk(dev_no));
env_set("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}