corenet_ds.h: Remove
This was missed when removing the platform. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
parent
e4573fef77
commit
fdffe6aae2
@ -1,369 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2009-2012 Freescale Semiconductor, Inc.
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* Copyright 2020-2021 NXP
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*/
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/*
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* Corenet DS style board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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#include "../board/freescale/common/ics307_clk.h"
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* Set 1M boot space */
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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/* High Level Configuration Options */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
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#else
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
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#endif
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#define CONFIG_SYS_L3_SIZE (1024 << 10)
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#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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#endif
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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/*
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* Local Bus Definitions
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*/
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/* Set the local bus clock 1/8 of platform clock */
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#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
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#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
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#ifdef CONFIG_PHYS_64BIT
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#define PIXIS_BASE_PHYS 0xfffdf0000ull
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#else
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#define PIXIS_BASE_PHYS PIXIS_BASE
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#endif
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#define PIXIS_LBMAP_SWITCH 7
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#define PIXIS_LBMAP_MASK 0xf0
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#define PIXIS_LBMAP_SHIFT 4
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#define PIXIS_LBMAP_ALTBANK 0x40
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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/* Nand Flash */
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#ifdef CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* NAND flash config */
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#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
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| OR_FCM_PGS /* Large Page*/ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#endif /* CONFIG_NAND_FSL_ELBC */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_HWCONFIG
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/* I2C */
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/*
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* RapidIO
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
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#else
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
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#endif
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#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
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/*
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* for slave u-boot IMAGE instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
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/*
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* for slave UCODE and ENV instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
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/* slave core release by master*/
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#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
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#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
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/*
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* SRIO_PCIE_BOOT - SLAVE
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*/
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
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#endif
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/*
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* eSPI - Enhanced SPI
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*/
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
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/* controller 4, Base address 203000 */
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#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
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#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
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/* Qman/Bman */
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#define CONFIG_SYS_BMAN_NUM_PORTALS 10
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
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#else
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#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
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#endif
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
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#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
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CONFIG_SYS_BMAN_CENA_SIZE)
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#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_QMAN_NUM_PORTALS 10
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
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#else
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#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
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#endif
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
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#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
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CONFIG_SYS_QMAN_CENA_SIZE)
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#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_DPAA_PME
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#ifdef CONFIG_FMAN_ENET
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#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
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#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
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#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
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#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
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#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
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#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
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#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
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#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
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#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
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#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
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#define CONFIG_SYS_TBIPA_VALUE 8
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#endif
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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/*
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* Miscellaneous configurable options
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*/
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
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/*
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* Environment Configuration
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*/
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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#ifdef CONFIG_TARGET_P4080DS
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#define __USB_PHY_TYPE ulpi
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#else
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#define __USB_PHY_TYPE utmi
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
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"bank_intlv=cs0_cs1;" \
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"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
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"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot && " \
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"protect off $ubootaddr +$filesize && " \
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"erase $ubootaddr +$filesize && " \
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"cp.b $loadaddr $ubootaddr $filesize && " \
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"protect on $ubootaddr +$filesize && " \
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"cmp.b $loadaddr $ubootaddr $filesize\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=p4080ds/ramdisk.uboot\0" \
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"fdtaddr=1e00000\0" \
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"fdtfile=p4080ds/p4080ds.dtb\0" \
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"bdev=sda3\0"
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#include <asm/fsl_secure_boot.h>
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#endif /* __CONFIG_H */
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