phy: nuvoton: add NPCM7xx phy control driver
add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
parent
1cf4e79f57
commit
fdd08f896b
@ -274,6 +274,13 @@ config PHY_MTK_TPHY
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multi-ports is first version, otherwise is second veriosn,
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so you can easily distinguish them by banks layout.
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config PHY_NPCM_USB
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bool "Nuvoton NPCM USB PHY support"
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depends on PHY
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depends on ARCH_NPCM
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help
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Support the USB PHY in NPCM SoCs
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config PHY_IMX8MQ_USB
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bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver"
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depends on PHY
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@ -37,6 +37,7 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
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obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
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obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
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obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
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obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
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obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
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obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
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obj-y += cadence/
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215
drivers/phy/phy-npcm-usb.c
Normal file
215
drivers/phy/phy-npcm-usb.c
Normal file
@ -0,0 +1,215 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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/* GCR Register Offsets */
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#define GCR_INTCR3 0x9C
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#define GCR_USB1PHYCTL 0x140
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#define GCR_USB2PHYCTL 0x144
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#define GCR_USB3PHYCTL 0x148
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/* USBnPHYCTL bit fields */
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#define PHYCTL_RS BIT(28)
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#define USBPHY2SW GENMASK(13, 12)
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#define USBPHY3SW GENMASK(15, 14)
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#define USBPHY2SW_DEV9_PHY1 FIELD_PREP(USBPHY2SW, 0)
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#define USBPHY2SW_HOST1 FIELD_PREP(USBPHY2SW, 1)
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#define USBPHY2SW_DEV9_PHY2 FIELD_PREP(USBPHY2SW, 3)
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#define USBPHY3SW_DEV8_PHY1 FIELD_PREP(USBPHY3SW, 0)
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#define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1)
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#define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3)
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enum controller_id {
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UDC0_7,
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UDC8,
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UDC9,
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USBH1,
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USBH2,
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};
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enum phy_id {
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PHY1 = 1,
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PHY2,
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PHY3,
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};
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/* Phy Switch Settings */
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#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */
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#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */
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#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */
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#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */
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#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */
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#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */
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#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */
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struct npcm_usbphy {
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struct regmap *syscon;
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u8 id;
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u16 phy_switch; /* (phy_id << 8) | controller_id */
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};
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static int npcm_usb_phy_init(struct phy *phy)
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{
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struct npcm_usbphy *priv = dev_get_priv(phy->dev);
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struct reset_ctl reset;
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int ret;
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ret = reset_get_by_index(phy->dev, 0, &reset);
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if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
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dev_err(phy->dev, "can't get phy reset ctrl (err %d)", ret);
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return ret;
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}
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/* setup PHY switch */
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switch (priv->phy_switch) {
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case USBD8PHY1:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
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USBPHY3SW_DEV8_PHY1);
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break;
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case USBD8PHY3:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
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USBPHY3SW_DEV8_PHY3);
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break;
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case USBD9PHY1:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
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USBPHY2SW_DEV9_PHY1);
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break;
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case USBD9PHY2:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
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USBPHY2SW_DEV9_PHY2);
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break;
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case USBH1PHY2:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
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USBPHY2SW_HOST1);
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break;
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case USBH2PHY3:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
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USBPHY3SW_HOST2);
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break;
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default:
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break;
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}
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/* reset phy */
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if (reset_valid(&reset))
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reset_assert(&reset);
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/* Wait for PHY clocks to stablize for 50us or more */
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udelay(100);
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/* release phy from reset */
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if (reset_valid(&reset))
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reset_deassert(&reset);
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/* PHY RS bit should be set after reset */
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switch (priv->id) {
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case PHY1:
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regmap_update_bits(priv->syscon, GCR_USB1PHYCTL, PHYCTL_RS, PHYCTL_RS);
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break;
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case PHY2:
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regmap_update_bits(priv->syscon, GCR_USB2PHYCTL, PHYCTL_RS, PHYCTL_RS);
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break;
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case PHY3:
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regmap_update_bits(priv->syscon, GCR_USB3PHYCTL, PHYCTL_RS, PHYCTL_RS);
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break;
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default:
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break;
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}
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return 0;
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}
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static int npcm_usb_phy_exit(struct phy *phy)
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{
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struct npcm_usbphy *priv = dev_get_priv(phy->dev);
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/* set PHY switch to default state */
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switch (priv->phy_switch) {
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case USBD8PHY1:
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case USBD8PHY3:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
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USBPHY3SW_HOST2);
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break;
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case USBD9PHY1:
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case USBD9PHY2:
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regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
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USBPHY2SW_HOST1);
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break;
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default:
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break;
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}
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return 0;
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}
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static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
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{
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struct npcm_usbphy *priv = dev_get_priv(phy->dev);
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u16 phy_switch;
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if (args->args_count < 1 || args->args[0] > USBH2)
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return -EINVAL;
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phy_switch = (priv->id << 8) | args->args[0];
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switch (phy_switch) {
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case USBD9PHY1:
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case USBH2PHY3:
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case USBD8PHY3:
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if (!IS_ENABLED(CONFIG_ARCH_NPCM8XX))
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return -EINVAL;
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case USBDPHY1:
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case USBD8PHY1:
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case USBD9PHY2:
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case USBH1PHY2:
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priv->phy_switch = phy_switch;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int npcm_usb_phy_probe(struct udevice *dev)
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{
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struct npcm_usbphy *priv = dev_get_priv(dev);
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priv->syscon = syscon_regmap_lookup_by_phandle(dev->parent, "syscon");
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if (IS_ERR(priv->syscon)) {
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dev_err(dev, "%s: unable to get syscon\n", __func__);
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return PTR_ERR(priv->syscon);
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}
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priv->id = dev_read_u32_default(dev, "reg", -1);
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return 0;
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}
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static const struct udevice_id npcm_phy_ids[] = {
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{ .compatible = "nuvoton,npcm845-usb-phy",},
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{ .compatible = "nuvoton,npcm750-usb-phy",},
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{ }
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};
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static struct phy_ops npcm_phy_ops = {
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.init = npcm_usb_phy_init,
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.exit = npcm_usb_phy_exit,
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.of_xlate = npcm_usb_phy_xlate,
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};
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U_BOOT_DRIVER(npcm_phy) = {
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.name = "npcm-usb-phy",
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.id = UCLASS_PHY,
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.of_match = npcm_phy_ids,
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.ops = &npcm_phy_ops,
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.probe = npcm_usb_phy_probe,
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.priv_auto = sizeof(struct npcm_usbphy),
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};
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