remoteproc: ipu: Add driver to bring up ipu
The driver enables IPU support. Basically enables the clocks, timers, watchdog timers and bare minimal MMU and supports loading the firmware from mmc. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix compile warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
This commit is contained in:
Keerthy
Tom Rini
parent
a03df89844
commit
fc6b41fefb
@ -539,6 +539,7 @@ F: drivers/phy/omap-usb2-phy.c
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F: drivers/phy/phy-ti-am654.c
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F: drivers/phy/phy-ti-am654.c
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F: drivers/phy/ti-pipe3-phy.c
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F: drivers/phy/ti-pipe3-phy.c
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F: drivers/ram/k3*
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F: drivers/ram/k3*
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F: drivers/remoteproc/ipu_rproc.c
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F: drivers/remoteproc/k3_system_controller.c
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F: drivers/remoteproc/k3_system_controller.c
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F: drivers/remoteproc/pruc_rpoc.c
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F: drivers/remoteproc/pruc_rpoc.c
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F: drivers/remoteproc/ti*
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F: drivers/remoteproc/ti*
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@ -92,4 +92,14 @@ config REMOTEPROC_TI_PRU
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help
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help
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Say 'y' here to add support for TI' K3 remoteproc driver.
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Say 'y' here to add support for TI' K3 remoteproc driver.
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config REMOTEPROC_TI_IPU
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bool "Support for TI's K3 based IPU remoteproc driver"
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select REMOTEPROC
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depends on DM
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depends on SPL_DRIVERS_MISC
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depends on SPL_FS_LOADER
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depends on OF_CONTROL
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help
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Say 'y' here to add support for TI' K3 remoteproc driver.
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endmenu
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endmenu
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@ -15,3 +15,4 @@ obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
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obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
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obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
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obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
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obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
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obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
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obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
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obj-$(CONFIG_REMOTEPROC_TI_IPU) += ipu_rproc.o
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759
drivers/remoteproc/ipu_rproc.c
Normal file
759
drivers/remoteproc/ipu_rproc.c
Normal file
@ -0,0 +1,759 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* IPU remoteproc driver for various SoCs
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Angela Stegmaier <angelabaker@ti.com>
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* Venkateswara Rao Mandela <venkat.mandela@ti.com>
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* Keerthy <j-keerthy@ti.com>
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*/
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#include <common.h>
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#include <hang.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <elf.h>
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#include <env.h>
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#include <dm/of_access.h>
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#include <fs_loader.h>
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#include <remoteproc.h>
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#include <errno.h>
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#include <clk.h>
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#include <reset.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <misc.h>
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#include <power-domain.h>
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#include <timer.h>
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#include <fs.h>
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#include <spl.h>
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#include <timer.h>
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#include <reset.h>
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#include <linux/bitmap.h>
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#define IPU1_LOAD_ADDR (0xa17ff000)
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#define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
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enum ipu_num {
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IPU1 = 0,
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IPU2,
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RPROC_END_ENUMS,
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};
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#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
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#define PAGE_SHIFT 12
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#define PAGESIZE_1M 0x0
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#define PAGESIZE_64K 0x1
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#define PAGESIZE_4K 0x2
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#define PAGESIZE_16M 0x3
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#define LE 0
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#define BE 1
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#define ELEMSIZE_8 0x0
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#define ELEMSIZE_16 0x1
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#define ELEMSIZE_32 0x2
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#define MIXED_TLB 0x0
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#define MIXED_CPU 0x1
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#define PGT_SMALLPAGE_SIZE 0x00001000
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#define PGT_LARGEPAGE_SIZE 0x00010000
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#define PGT_SECTION_SIZE 0x00100000
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#define PGT_SUPERSECTION_SIZE 0x01000000
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#define PGT_L1_DESC_PAGE 0x00001
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#define PGT_L1_DESC_SECTION 0x00002
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#define PGT_L1_DESC_SUPERSECTION 0x40002
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#define PGT_L1_DESC_PAGE_MASK 0xfffffC00
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#define PGT_L1_DESC_SECTION_MASK 0xfff00000
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#define PGT_L1_DESC_SUPERSECTION_MASK 0xff000000
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#define PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT 12
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#define PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT 16
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#define PGT_L1_DESC_SECTION_INDEX_SHIFT 20
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#define PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT 24
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#define PGT_L2_DESC_SMALLPAGE 0x02
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#define PGT_L2_DESC_LARGEPAGE 0x01
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#define PGT_L2_DESC_SMALLPAGE_MASK 0xfffff000
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#define PGT_L2_DESC_LARGEPAGE_MASK 0xffff0000
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/*
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* The memory for the page tables (256 KB per IPU) is placed just before
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* the carveout memories for the remote processors. 16 KB of memory is
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* needed for the L1 page table (4096 entries * 4 bytes per 1 MB section).
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* Any smaller page (64 KB or 4 KB) entries are supported through L2 page
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* tables (1 KB per table). The remaining 240 KB can provide support for
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* 240 L2 page tables. Any remoteproc firmware image requiring more than
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* 240 L2 page table entries would need more memory to be reserved.
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*/
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#define PAGE_TABLE_SIZE_L1 (0x00004000)
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#define PAGE_TABLE_SIZE_L2 (0x400)
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#define MAX_NUM_L2_PAGE_TABLES (240)
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#define PAGE_TABLE_SIZE_L2_TOTAL (MAX_NUM_L2_PAGE_TABLES * PAGE_TABLE_SIZE_L2)
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#define PAGE_TABLE_SIZE (PAGE_TABLE_SIZE_L1 + (PAGE_TABLE_SIZE_L2_TOTAL))
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/**
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* struct omap_rproc_mem - internal memory structure
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* @cpu_addr: MPU virtual address of the memory region
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* @bus_addr: bus address used to access the memory region
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* @dev_addr: device address of the memory region from DSP view
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* @size: size of the memory region
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*/
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struct omap_rproc_mem {
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void __iomem *cpu_addr;
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phys_addr_t bus_addr;
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u32 dev_addr;
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size_t size;
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};
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struct ipu_privdata {
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struct omap_rproc_mem mem;
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struct list_head mappings;
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const char *fw_name;
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u32 bootaddr;
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int id;
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struct udevice *rdev;
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};
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typedef int (*handle_resource_t) (void *, int offset, int avail);
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unsigned int *page_table_l1 = (unsigned int *)0x0;
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unsigned int *page_table_l2 = (unsigned int *)0x0;
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/*
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* Set maximum carveout size to 96 MB
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*/
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#define DRA7_RPROC_MAX_CO_SIZE (96 * 0x100000)
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/*
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* These global variables are used for deriving the MMU page tables. They
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* are initialized for each core with the appropriate values. The length
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* of the array mem_bitmap is set as per a 96 MB carveout which the
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* maximum set aside in the current memory map.
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*/
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unsigned long mem_base;
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unsigned long mem_size;
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unsigned long
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mem_bitmap[BITS_TO_LONGS(DRA7_RPROC_MAX_CO_SIZE >> PAGE_SHIFT)];
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unsigned long mem_count;
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unsigned int pgtable_l2_map[MAX_NUM_L2_PAGE_TABLES];
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unsigned int pgtable_l2_cnt;
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void *ipu_alloc_mem(struct udevice *dev, unsigned long len, unsigned long align)
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{
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unsigned long mask;
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unsigned long pageno;
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int count;
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count = ((len + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1)) >> PAGE_SHIFT;
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mask = (1 << align) - 1;
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pageno =
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bitmap_find_next_zero_area(mem_bitmap, mem_count, 0, count, mask);
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debug("%s: count %d mask %#lx pageno %#lx\n", __func__, count, mask,
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pageno);
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if (pageno >= mem_count) {
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debug("%s: %s Error allocating memory; "
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"Please check carveout size\n", __FILE__, __func__);
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return NULL;
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}
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bitmap_set(mem_bitmap, pageno, count);
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return (void *)(mem_base + (pageno << PAGE_SHIFT));
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}
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int find_pagesz(unsigned int virt, unsigned int phys, unsigned int len)
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{
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int pg_sz_ind = -1;
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unsigned int min_align = __ffs(virt);
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if (min_align > __ffs(phys))
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min_align = __ffs(phys);
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if (min_align >= PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT &&
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len >= 0x1000000) {
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pg_sz_ind = PAGESIZE_16M;
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goto ret_block;
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}
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if (min_align >= PGT_L1_DESC_SECTION_INDEX_SHIFT &&
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len >= 0x100000) {
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pg_sz_ind = PAGESIZE_1M;
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goto ret_block;
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}
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if (min_align >= PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT &&
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len >= 0x10000) {
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pg_sz_ind = PAGESIZE_64K;
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goto ret_block;
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}
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if (min_align >= PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT &&
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len >= 0x1000) {
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pg_sz_ind = PAGESIZE_4K;
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goto ret_block;
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}
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ret_block:
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return pg_sz_ind;
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}
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int get_l2_pg_tbl_addr(unsigned int virt, unsigned int *pg_tbl_addr)
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{
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int ret = -1;
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int i = 0;
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int match_found = 0;
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unsigned int tag = (virt & PGT_L1_DESC_SECTION_MASK);
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*pg_tbl_addr = 0;
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for (i = 0; (i < pgtable_l2_cnt) && (match_found == 0); i++) {
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if (tag == pgtable_l2_map[i]) {
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*pg_tbl_addr =
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((unsigned int)page_table_l2) +
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(i * PAGE_TABLE_SIZE_L2);
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match_found = 1;
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ret = 0;
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}
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}
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if (match_found == 0 && i < MAX_NUM_L2_PAGE_TABLES) {
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pgtable_l2_map[i] = tag;
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pgtable_l2_cnt++;
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*pg_tbl_addr =
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((unsigned int)page_table_l2) + (i * PAGE_TABLE_SIZE_L2);
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ret = 0;
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}
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return ret;
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}
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int
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config_l2_pagetable(unsigned int virt, unsigned int phys,
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unsigned int pg_sz, unsigned int pg_tbl_addr)
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{
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int ret = -1;
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unsigned int desc = 0;
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int i = 0;
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unsigned int *pg_tbl = (unsigned int *)pg_tbl_addr;
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/*
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* Pick bit 19:12 of the virtual address as index
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*/
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unsigned int index = (virt & (~PGT_L1_DESC_SECTION_MASK)) >> PAGE_SHIFT;
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switch (pg_sz) {
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case PAGESIZE_64K:
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desc =
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(phys & PGT_L2_DESC_LARGEPAGE_MASK) | PGT_L2_DESC_LARGEPAGE;
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for (i = 0; i < 16; i++)
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pg_tbl[index + i] = desc;
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ret = 0;
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break;
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case PAGESIZE_4K:
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desc =
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(phys & PGT_L2_DESC_SMALLPAGE_MASK) | PGT_L2_DESC_SMALLPAGE;
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pg_tbl[index] = desc;
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ret = 0;
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break;
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default:
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break;
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}
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return ret;
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}
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unsigned int
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ipu_config_pagetable(struct udevice *dev, unsigned int virt, unsigned int phys,
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unsigned int len)
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{
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unsigned int index;
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unsigned int l = len;
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unsigned int desc;
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int pg_sz = 0;
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int i = 0, err = 0;
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unsigned int pg_tbl_l2_addr = 0;
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unsigned int tmp_pgsz;
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if ((len & 0x0FFF) != 0)
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return 0;
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while (l > 0) {
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pg_sz = find_pagesz(virt, phys, l);
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index = virt >> PGT_L1_DESC_SECTION_INDEX_SHIFT;
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switch (pg_sz) {
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/*
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* 16 MB super section
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*/
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case PAGESIZE_16M:
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/*
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* Program the next 16 descriptors
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*/
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desc =
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(phys & PGT_L1_DESC_SUPERSECTION_MASK) |
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PGT_L1_DESC_SUPERSECTION;
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for (i = 0; i < 16; i++)
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page_table_l1[index + i] = desc;
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l -= PGT_SUPERSECTION_SIZE;
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phys += PGT_SUPERSECTION_SIZE;
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virt += PGT_SUPERSECTION_SIZE;
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break;
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/*
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* 1 MB section
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*/
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case PAGESIZE_1M:
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desc =
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(phys & PGT_L1_DESC_SECTION_MASK) |
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PGT_L1_DESC_SECTION;
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page_table_l1[index] = desc;
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l -= PGT_SECTION_SIZE;
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phys += PGT_SECTION_SIZE;
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virt += PGT_SECTION_SIZE;
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break;
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/*
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* 64 KB large page
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*/
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case PAGESIZE_64K:
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case PAGESIZE_4K:
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if (pg_sz == PAGESIZE_64K)
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tmp_pgsz = 0x10000;
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else
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tmp_pgsz = 0x1000;
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err = get_l2_pg_tbl_addr(virt, &pg_tbl_l2_addr);
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if (err != 0) {
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debug
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||||||
|
("Unable to get level 2 PT address\n");
|
||||||
|
hang();
|
||||||
|
}
|
||||||
|
err =
|
||||||
|
config_l2_pagetable(virt, phys, pg_sz,
|
||||||
|
pg_tbl_l2_addr);
|
||||||
|
desc =
|
||||||
|
(pg_tbl_l2_addr & PGT_L1_DESC_PAGE_MASK) |
|
||||||
|
PGT_L1_DESC_PAGE;
|
||||||
|
page_table_l1[index] = desc;
|
||||||
|
l -= tmp_pgsz;
|
||||||
|
phys += tmp_pgsz;
|
||||||
|
virt += tmp_pgsz;
|
||||||
|
break;
|
||||||
|
case -1:
|
||||||
|
default:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
int da_to_pa(struct udevice *dev, int da)
|
||||||
|
{
|
||||||
|
struct rproc_mem_entry *maps = NULL;
|
||||||
|
struct ipu_privdata *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
list_for_each_entry(maps, &priv->mappings, node) {
|
||||||
|
if (da >= maps->da && da < (maps->da + maps->len))
|
||||||
|
return maps->dma + (da - maps->da);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 ipu_config_mmu(u32 core_id, struct rproc *cfg)
|
||||||
|
{
|
||||||
|
u32 i = 0;
|
||||||
|
u32 reg = 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear the entire pagetable location before programming the
|
||||||
|
* address into the MMU
|
||||||
|
*/
|
||||||
|
memset((void *)cfg->page_table_addr, 0x00, PAGE_TABLE_SIZE);
|
||||||
|
|
||||||
|
for (i = 0; i < cfg->num_iommus; i++) {
|
||||||
|
u32 mmu_base = cfg->mmu_base_addr[i];
|
||||||
|
|
||||||
|
__raw_writel((int)cfg->page_table_addr, mmu_base + 0x4c);
|
||||||
|
reg = __raw_readl(mmu_base + 0x88);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* enable bus-error back
|
||||||
|
*/
|
||||||
|
__raw_writel(reg | 0x1, mmu_base + 0x88);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable the MMU IRQs during MMU programming for the
|
||||||
|
* late attachcase. This is to allow the MMU fault to be
|
||||||
|
* detected by the kernel.
|
||||||
|
*
|
||||||
|
* MULTIHITFAULT|EMMUMISS|TRANSLATIONFAULT|TABLEWALKFAULT
|
||||||
|
*/
|
||||||
|
__raw_writel(0x1E, mmu_base + 0x1c);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* emutlbupdate|TWLENABLE|MMUENABLE
|
||||||
|
*/
|
||||||
|
__raw_writel(0x6, mmu_base + 0x44);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum ipu_mem - PRU core memory range identifiers
|
||||||
|
*/
|
||||||
|
enum ipu_mem {
|
||||||
|
PRU_MEM_IRAM = 0,
|
||||||
|
PRU_MEM_CTRL,
|
||||||
|
PRU_MEM_DEBUG,
|
||||||
|
PRU_MEM_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int ipu_start(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct ipu_privdata *priv;
|
||||||
|
struct reset_ctl reset;
|
||||||
|
struct rproc *cfg = NULL;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
cfg = rproc_cfg_arr[priv->id];
|
||||||
|
if (cfg->config_peripherals)
|
||||||
|
cfg->config_peripherals(priv->id, cfg);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Start running the remote core
|
||||||
|
*/
|
||||||
|
ret = reset_get_by_index(dev, 0, &reset);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(dev, "%s: error getting reset index %d\n", __func__, 0);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = reset_deassert(&reset);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(dev, "%s: error deasserting reset %d\n", __func__, 0);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = reset_get_by_index(dev, 1, &reset);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(dev, "%s: error getting reset index %d\n", __func__, 1);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = reset_deassert(&reset);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(dev, "%s: error deasserting reset %d\n", __func__, 1);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ipu_stop(struct udevice *dev)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ipu_init() - Initialize the remote processor
|
||||||
|
* @dev: rproc device pointer
|
||||||
|
*
|
||||||
|
* Return: 0 if all went ok, else return appropriate error
|
||||||
|
*/
|
||||||
|
static int ipu_init(struct udevice *dev)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ipu_add_res(struct udevice *dev, struct rproc_mem_entry *mapping)
|
||||||
|
{
|
||||||
|
struct ipu_privdata *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
list_add_tail(&mapping->node, &priv->mappings);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ipu_load(struct udevice *dev, ulong addr, ulong size)
|
||||||
|
{
|
||||||
|
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
|
||||||
|
Elf32_Phdr *phdr; /* Program header structure pointer */
|
||||||
|
Elf32_Phdr proghdr;
|
||||||
|
int va;
|
||||||
|
int pa;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
ehdr = (Elf32_Ehdr *)addr;
|
||||||
|
phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
|
||||||
|
/*
|
||||||
|
* Load each program header
|
||||||
|
*/
|
||||||
|
for (i = 0; i < ehdr->e_phnum; ++i) {
|
||||||
|
memcpy(&proghdr, phdr, sizeof(Elf32_Phdr));
|
||||||
|
|
||||||
|
if (proghdr.p_type != PT_LOAD) {
|
||||||
|
++phdr;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
va = proghdr.p_paddr;
|
||||||
|
pa = da_to_pa(dev, va);
|
||||||
|
if (pa)
|
||||||
|
proghdr.p_paddr = pa;
|
||||||
|
|
||||||
|
void *dst = (void *)(uintptr_t)proghdr.p_paddr;
|
||||||
|
void *src = (void *)addr + proghdr.p_offset;
|
||||||
|
|
||||||
|
debug("Loading phdr %i to 0x%p (%i bytes)\n", i, dst,
|
||||||
|
proghdr.p_filesz);
|
||||||
|
if (proghdr.p_filesz)
|
||||||
|
memcpy(dst, src, proghdr.p_filesz);
|
||||||
|
|
||||||
|
flush_cache((unsigned long)dst, proghdr.p_memsz);
|
||||||
|
|
||||||
|
++phdr;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_rproc_ops ipu_ops = {
|
||||||
|
.init = ipu_init,
|
||||||
|
.start = ipu_start,
|
||||||
|
.stop = ipu_stop,
|
||||||
|
.load = ipu_load,
|
||||||
|
.add_res = ipu_add_res,
|
||||||
|
.config_pagetable = ipu_config_pagetable,
|
||||||
|
.alloc_mem = ipu_alloc_mem,
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If the remotecore binary expects any peripherals to be setup before it has
|
||||||
|
* booted, configure them here.
|
||||||
|
*
|
||||||
|
* These functions are left empty by default as their operation is usecase
|
||||||
|
* specific.
|
||||||
|
*/
|
||||||
|
|
||||||
|
u32 ipu1_config_peripherals(u32 core_id, struct rproc *cfg)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 ipu2_config_peripherals(u32 core_id, struct rproc *cfg)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct rproc_intmem_to_l3_mapping ipu1_intmem_to_l3_mapping = {
|
||||||
|
.num_entries = 1,
|
||||||
|
.mappings = {
|
||||||
|
/*
|
||||||
|
* L2 SRAM
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
.priv_addr = 0x55020000,
|
||||||
|
.l3_addr = 0x58820000,
|
||||||
|
.len = (64 * 1024)},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
struct rproc_intmem_to_l3_mapping ipu2_intmem_to_l3_mapping = {
|
||||||
|
.num_entries = 1,
|
||||||
|
.mappings = {
|
||||||
|
/*
|
||||||
|
* L2 SRAM
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
.priv_addr = 0x55020000,
|
||||||
|
.l3_addr = 0x55020000,
|
||||||
|
.len = (64 * 1024)},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
struct rproc ipu1_config = {
|
||||||
|
.num_iommus = 1,
|
||||||
|
.mmu_base_addr = {0x58882000, 0},
|
||||||
|
.load_addr = IPU1_LOAD_ADDR,
|
||||||
|
.core_name = "IPU1",
|
||||||
|
.firmware_name = "dra7-ipu1-fw.xem4",
|
||||||
|
.config_mmu = ipu_config_mmu,
|
||||||
|
.config_peripherals = ipu1_config_peripherals,
|
||||||
|
.intmem_to_l3_mapping = &ipu1_intmem_to_l3_mapping
|
||||||
|
};
|
||||||
|
|
||||||
|
struct rproc ipu2_config = {
|
||||||
|
.num_iommus = 1,
|
||||||
|
.mmu_base_addr = {0x55082000, 0},
|
||||||
|
.load_addr = IPU2_LOAD_ADDR,
|
||||||
|
.core_name = "IPU2",
|
||||||
|
.firmware_name = "dra7-ipu2-fw.xem4",
|
||||||
|
.config_mmu = ipu_config_mmu,
|
||||||
|
.config_peripherals = ipu2_config_peripherals,
|
||||||
|
.intmem_to_l3_mapping = &ipu2_intmem_to_l3_mapping
|
||||||
|
};
|
||||||
|
|
||||||
|
struct rproc *rproc_cfg_arr[2] = {
|
||||||
|
[IPU2] = &ipu2_config,
|
||||||
|
[IPU1] = &ipu1_config,
|
||||||
|
};
|
||||||
|
|
||||||
|
u32 spl_pre_boot_core(struct udevice *dev, u32 core_id)
|
||||||
|
{
|
||||||
|
struct rproc *cfg = NULL;
|
||||||
|
unsigned long load_elf_status = 0;
|
||||||
|
int tablesz;
|
||||||
|
|
||||||
|
cfg = rproc_cfg_arr[core_id];
|
||||||
|
/*
|
||||||
|
* Check for valid elf image
|
||||||
|
*/
|
||||||
|
if (!valid_elf_image(cfg->load_addr))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
if (rproc_find_resource_table(dev, cfg->load_addr, &tablesz))
|
||||||
|
cfg->has_rsc_table = 1;
|
||||||
|
else
|
||||||
|
cfg->has_rsc_table = 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure the MMU
|
||||||
|
*/
|
||||||
|
if (cfg->config_mmu && cfg->has_rsc_table)
|
||||||
|
cfg->config_mmu(core_id, cfg);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Load the remote core. Fill the page table of the first(possibly
|
||||||
|
* only) IOMMU during ELF loading. Copy the page table to the second
|
||||||
|
* IOMMU before running the remote core.
|
||||||
|
*/
|
||||||
|
|
||||||
|
page_table_l1 = (unsigned int *)cfg->page_table_addr;
|
||||||
|
page_table_l2 =
|
||||||
|
(unsigned int *)(cfg->page_table_addr + PAGE_TABLE_SIZE_L1);
|
||||||
|
mem_base = cfg->cma_base;
|
||||||
|
mem_size = cfg->cma_size;
|
||||||
|
memset(mem_bitmap, 0x00, sizeof(mem_bitmap));
|
||||||
|
mem_count = (cfg->cma_size >> PAGE_SHIFT);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear variables used for level 2 page table allocation
|
||||||
|
*/
|
||||||
|
memset(pgtable_l2_map, 0x00, sizeof(pgtable_l2_map));
|
||||||
|
pgtable_l2_cnt = 0;
|
||||||
|
|
||||||
|
load_elf_status = rproc_parse_resource_table(dev, cfg);
|
||||||
|
if (load_elf_status == 0) {
|
||||||
|
debug("load_elf_image_phdr returned error for core %s\n",
|
||||||
|
cfg->core_name);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
flush_cache(cfg->page_table_addr, PAGE_TABLE_SIZE);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static fdt_addr_t ipu_parse_mem_nodes(struct udevice *dev, char *name,
|
||||||
|
int privid, fdt_size_t *sizep)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u32 sp;
|
||||||
|
ofnode mem_node;
|
||||||
|
|
||||||
|
ret = ofnode_read_u32(dev_ofnode(dev), name, &sp);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "memory-region node fetch failed %d\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
mem_node = ofnode_get_by_phandle(sp);
|
||||||
|
if (!ofnode_valid(mem_node))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return ofnode_get_addr_size_index(mem_node, 0, sizep);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ipu_probe() - Basic probe
|
||||||
|
* @dev: corresponding k3 remote processor device
|
||||||
|
*
|
||||||
|
* Return: 0 if all goes good, else appropriate error message.
|
||||||
|
*/
|
||||||
|
static int ipu_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct ipu_privdata *priv;
|
||||||
|
struct rproc *cfg = NULL;
|
||||||
|
struct reset_ctl reset;
|
||||||
|
static const char *const ipu_mem_names[] = { "l2ram" };
|
||||||
|
int ret;
|
||||||
|
fdt_size_t sizep;
|
||||||
|
|
||||||
|
priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
priv->mem.bus_addr =
|
||||||
|
devfdt_get_addr_size_name(dev,
|
||||||
|
ipu_mem_names[0],
|
||||||
|
(fdt_addr_t *)&priv->mem.size);
|
||||||
|
|
||||||
|
ret = reset_get_by_index(dev, 2, &reset);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(dev, "%s: error getting reset index %d\n", __func__, 2);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = reset_deassert(&reset);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(dev, "%s: error deasserting reset %d\n", __func__, 2);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (priv->mem.bus_addr == FDT_ADDR_T_NONE) {
|
||||||
|
dev_err(dev, "%s bus address not found\n", ipu_mem_names[0]);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
priv->mem.cpu_addr = map_physmem(priv->mem.bus_addr,
|
||||||
|
priv->mem.size, MAP_NOCACHE);
|
||||||
|
|
||||||
|
if (devfdt_get_addr(dev) == 0x58820000)
|
||||||
|
priv->id = 0;
|
||||||
|
else
|
||||||
|
priv->id = 1;
|
||||||
|
|
||||||
|
cfg = rproc_cfg_arr[priv->id];
|
||||||
|
cfg->cma_base = ipu_parse_mem_nodes(dev, "memory-region", priv->id,
|
||||||
|
&sizep);
|
||||||
|
cfg->cma_size = sizep;
|
||||||
|
|
||||||
|
cfg->page_table_addr = ipu_parse_mem_nodes(dev, "pg-tbl", priv->id,
|
||||||
|
&sizep);
|
||||||
|
|
||||||
|
dev_info(dev,
|
||||||
|
"ID %d memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
|
||||||
|
priv->id, ipu_mem_names[0], &priv->mem.bus_addr,
|
||||||
|
priv->mem.size, priv->mem.cpu_addr, priv->mem.dev_addr);
|
||||||
|
|
||||||
|
INIT_LIST_HEAD(&priv->mappings);
|
||||||
|
if (spl_pre_boot_core(dev, priv->id))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct udevice_id ipu_ids[] = {
|
||||||
|
{.compatible = "ti,dra7-ipu"},
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(ipu) = {
|
||||||
|
.name = "ipu",
|
||||||
|
.of_match = ipu_ids,
|
||||||
|
.id = UCLASS_REMOTEPROC,
|
||||||
|
.ops = &ipu_ops,
|
||||||
|
.probe = ipu_probe,
|
||||||
|
.priv_auto = sizeof(struct ipu_privdata),
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue
Block a user