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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini
2016-05-24 13:42:03 -04:00
parent 2ee490a024 bc323b3fa7
commit fc15b9beed
55 changed files with 631 additions and 218 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/freescale/c29xpcie/c29xpcie.c
View File

@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
+ offset * 0x20000)) >= 0) {
+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
fdt_del_node(blob, nodeoff);
offset++;
}

6
board/freescale/common/ls102xa_stream_id.c
View File

@@ -10,11 +10,11 @@
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
for (i = 0; i < num; i++)
out_be32(scfg + id[i].offset, id[i].stream_id);
out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
}
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
@@ -28,6 +28,6 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
else
liodn = tbl[i].id[0];
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
out_le32((u32 *)(tbl[i].reg_offset), liodn);
}
}

1
board/freescale/ls1043aqds/ddr.c
View File

@@ -116,6 +116,7 @@ phys_size_t initdram(int board_type)
dram_size = fsl_ddr_sdram();
#endif
erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();

2
board/freescale/ls1043aqds/ddr.h
View File

@@ -7,6 +7,8 @@
#ifndef __DDR_H__
#define __DDR_H__
extern void erratum_a008850_post(void);
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;

12
board/freescale/ls1043aqds/ls1043aqds.c
View File

@@ -307,14 +307,6 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
CONFIG_SYS_CCI400_ADDR;
/* Set CCI-400 control override register to enable barrier
* transaction */
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
@@ -325,10 +317,6 @@ int board_init(void)
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
return 0;
}

26
board/freescale/ls1043ardb/cpld.c
View File

@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
u8 reg5 = (u8)(reg >> 1);
u8 reg6 = (u8)(reg & 1);
u8 reg7 = CPLD_READ(vbank);
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
cpld_rev_bit(&reg5);
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
CPLD_WRITE(cfg_rcw_src1, reg5);
CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
CPLD_WRITE(global_rst, 1);
u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
u8 reg5 = (u8)(reg >> 1);
u8 reg6 = (u8)(reg & 1);
cpld_rev_bit(&reg5);
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
CPLD_WRITE(cfg_rcw_src1, reg5);
CPLD_WRITE(cfg_rcw_src2, reg6);
CPLD_WRITE(vbank, 0);
CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void)

1
board/freescale/ls1043ardb/cpld.h
View File

@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
#define CPLD_SW_MUX_BANK_SEL 0x40
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif

2
board/freescale/ls1043ardb/ddr.c
View File

@@ -177,6 +177,8 @@ phys_size_t initdram(int board_type)
#else
dram_size = fsl_ddr_sdram_size();
#endif
erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#endif

3
board/freescale/ls1043ardb/ddr.h
View File

@@ -6,6 +6,9 @@
#ifndef __DDR_H__
#define __DDR_H__
extern void erratum_a008850_post(void);
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;

21
board/freescale/ls1043ardb/ls1043ardb.c
View File

@@ -19,7 +19,6 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <environment.h>
#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
@@ -31,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
u32 cfg_rcw_src;
u16 cfg_rcw_src;
#endif
u32 sd1refclk_sel;
u8 sd1refclk_sel;
printf("Board: LS1043ARDB, boot from ");
@@ -83,22 +82,12 @@ int board_early_init_f(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
/*
* Set CCI-400 control override register to enable barrier
* transaction
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
@@ -106,6 +95,8 @@ int board_init(void)
#ifdef CONFIG_U_QE
u_qe_init();
#endif
/* invert AQR105 IRQ pins polarity */
out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
return 0;
}

2
board/freescale/ls2080aqds/MAINTAINERS
View File

@@ -1,5 +1,5 @@
LS2080A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c

2
board/freescale/ls2080ardb/MAINTAINERS
View File

@@ -1,5 +1,5 @@
LS2080A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c

6
board/freescale/ls2080ardb/ddr.h
View File

@@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
{2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
{2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
{2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
{2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
{2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};