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net: sh-eth: Change read/write() param to struct sh_eth_info

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This changes Change structure used in sh_eth_read and sh_eth_write function
from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert
to Driver Model.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Nobuhiro Iwamatsu 2017-12-01 08:10:32 +09:00 committed by Joe Hershberger
parent 9b5f9ecf6e
commit fbfb511548
2 changed files with 75 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

119
drivers/net/sh_eth.c
View File

@ -86,8 +86,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
/* Restart the transmitter if disabled */ /* Restart the transmitter if disabled */
if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
sh_eth_write(eth, EDTRR_TRNS, EDTRR); sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
/* Wait until packet is transmitted */ /* Wait until packet is transmitted */
timeout = TIMEOUT_CNT; timeout = TIMEOUT_CNT;
@ -147,24 +147,25 @@ int sh_eth_recv(struct eth_device *dev)
} }
/* Restart the receiver if disabled */ /* Restart the receiver if disabled */
if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
sh_eth_write(eth, EDRRR_R, EDRRR); sh_eth_write(port_info, EDRRR_R, EDRRR);
return len; return len;
} }
static int sh_eth_reset(struct sh_eth_dev *eth) static int sh_eth_reset(struct sh_eth_dev *eth)
{ {
struct sh_eth_info *port_info = &eth->port_info[eth->port];
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i; int ret = 0, i;
/* Start e-dmac transmitter and receiver */ /* Start e-dmac transmitter and receiver */
sh_eth_write(eth, EDSR_ENALL, EDSR); sh_eth_write(port_info, EDSR_ENALL, EDSR);
/* Perform a software reset and wait for it to complete */ /* Perform a software reset and wait for it to complete */
sh_eth_write(eth, EDMR_SRST, EDMR); sh_eth_write(port_info, EDMR_SRST, EDMR);
for (i = 0; i < TIMEOUT_CNT; i++) { for (i = 0; i < TIMEOUT_CNT; i++) {
if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
break; break;
udelay(1000); udelay(1000);
} }
@ -176,9 +177,10 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
return ret; return ret;
#else #else
sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
udelay(3000); udelay(3000);
sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); sh_eth_write(port_info,
sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
return 0; return 0;
#endif #endif
@ -226,11 +228,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
* Point the controller to the tx descriptor list. Must use physical * Point the controller to the tx descriptor list. Must use physical
* addresses * addresses
*/ */
sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
#endif #endif
err: err:
@ -293,11 +295,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
cur_rx_desc->rd0 |= RD_RDLE; cur_rx_desc->rd0 |= RD_RDLE;
/* Point the controller to the rx descriptor list */ /* Point the controller to the rx descriptor list */
sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
sh_eth_write(eth, RDFFR_RDLF, RDFFR); sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
#endif #endif
return ret; return ret;
@ -382,45 +384,45 @@ static int sh_eth_config(struct sh_eth_dev *eth)
struct phy_device *phy; struct phy_device *phy;
/* Configure e-dmac registers */ /* Configure e-dmac registers */
sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
(EMDR_DESC | EDMR_EL), EDMR); (EMDR_DESC | EDMR_EL), EDMR);
sh_eth_write(eth, 0, EESIPR); sh_eth_write(port_info, 0, EESIPR);
sh_eth_write(eth, 0, TRSCER); sh_eth_write(port_info, 0, TRSCER);
sh_eth_write(eth, 0, TFTR); sh_eth_write(port_info, 0, TFTR);
sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
sh_eth_write(eth, RMCR_RST, RMCR); sh_eth_write(port_info, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, 0, RPADIR); sh_eth_write(port_info, 0, RPADIR);
#endif #endif
sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
/* Configure e-mac registers */ /* Configure e-mac registers */
sh_eth_write(eth, 0, ECSIPR); sh_eth_write(port_info, 0, ECSIPR);
/* Set Mac address */ /* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
dev->enetaddr[2] << 8 | dev->enetaddr[3]; dev->enetaddr[2] << 8 | dev->enetaddr[3];
sh_eth_write(eth, val, MAHR); sh_eth_write(port_info, val, MAHR);
val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
sh_eth_write(eth, val, MALR); sh_eth_write(port_info, val, MALR);
sh_eth_write(eth, RFLR_RFL_MIN, RFLR); sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER) #if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, 0, PIPR); sh_eth_write(port_info, 0, PIPR);
#endif #endif
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, APR_AP, APR); sh_eth_write(port_info, APR_AP, APR);
sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(port_info, MPR_MP, MPR);
sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
#endif #endif
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif #endif
/* Configure phy */ /* Configure phy */
ret = sh_eth_phy_config(eth); ret = sh_eth_phy_config(eth);
@ -441,9 +443,9 @@ static int sh_eth_config(struct sh_eth_dev *eth)
if (phy->speed == 100) { if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/"); printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER) #if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, GECMR_100B, GECMR); sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE); sh_eth_write(port_info, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794) defined(CONFIG_R8A7794)
@ -452,27 +454,27 @@ static int sh_eth_config(struct sh_eth_dev *eth)
} else if (phy->speed == 10) { } else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/"); printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER) #if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, GECMR_10B, GECMR); sh_eth_write(port_info, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 0, RTRATE); sh_eth_write(port_info, 0, RTRATE);
#endif #endif
} }
#if defined(SH_ETH_TYPE_GETHER) #if defined(SH_ETH_TYPE_GETHER)
else if (phy->speed == 1000) { else if (phy->speed == 1000) {
printf(SHETHER_NAME ": 1000Base/"); printf(SHETHER_NAME ": 1000Base/");
sh_eth_write(eth, GECMR_1000B, GECMR); sh_eth_write(port_info, GECMR_1000B, GECMR);
} }
#endif #endif
/* Check if full duplex mode is supported by the phy */ /* Check if full duplex mode is supported by the phy */
if (phy->duplex) { if (phy->duplex) {
printf("Full\n"); printf("Full\n");
sh_eth_write(eth, sh_eth_write(port_info,
val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM), val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
ECMR); ECMR);
} else { } else {
printf("Half\n"); printf("Half\n");
sh_eth_write(eth, sh_eth_write(port_info,
val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE), val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
ECMR); ECMR);
} }
@ -485,16 +487,20 @@ err_phy_cfg:
static void sh_eth_start(struct sh_eth_dev *eth) static void sh_eth_start(struct sh_eth_dev *eth)
{ {
struct sh_eth_info *port_info = &eth->port_info[eth->port];
/* /*
* Enable the e-dmac receiver only. The transmitter will be enabled when * Enable the e-dmac receiver only. The transmitter will be enabled when
* we have something to transmit * we have something to transmit
*/ */
sh_eth_write(eth, EDRRR_R, EDRRR); sh_eth_write(port_info, EDRRR_R, EDRRR);
} }
static void sh_eth_stop(struct sh_eth_dev *eth) static void sh_eth_stop(struct sh_eth_dev *eth)
{ {
sh_eth_write(eth, ~EDRRR_R, EDRRR); struct sh_eth_info *port_info = &eth->port_info[eth->port];
sh_eth_write(port_info, ~EDRRR_R, EDRRR);
} }
int sh_eth_init(struct eth_device *dev, bd_t *bd) int sh_eth_init(struct eth_device *dev, bd_t *bd)
@ -558,6 +564,8 @@ int sh_eth_initialize(bd_t *bd)
eth->port = CONFIG_SH_ETHER_USE_PORT; eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
dev->priv = (void *)eth; dev->priv = (void *)eth;
dev->iobase = 0; dev->iobase = 0;
@ -609,8 +617,9 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{ {
struct sh_eth_dev *eth = bus->priv; struct sh_eth_dev *eth = bus->priv;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
return 0; return 0;
} }
@ -618,8 +627,9 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{ {
struct sh_eth_dev *eth = bus->priv; struct sh_eth_dev *eth = bus->priv;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
return 0; return 0;
} }
@ -627,11 +637,14 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{ {
struct sh_eth_dev *eth = bus->priv; struct sh_eth_dev *eth = bus->priv;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
if (v) if (v)
sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); sh_eth_write(port_info,
sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
else else
sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); sh_eth_write(port_info,
sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
return 0; return 0;
} }
@ -639,8 +652,9 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{ {
struct sh_eth_dev *eth = bus->priv; struct sh_eth_dev *eth = bus->priv;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
return 0; return 0;
} }
@ -648,11 +662,14 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{ {
struct sh_eth_dev *eth = bus->priv; struct sh_eth_dev *eth = bus->priv;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
if (v) if (v)
sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); sh_eth_write(port_info,
sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
else else
sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); sh_eth_write(port_info,
sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
return 0; return 0;
} }

13
drivers/net/sh_eth.h
View File

@ -92,6 +92,7 @@ struct sh_eth_info {
u8 phy_addr; u8 phy_addr;
struct eth_device *dev; struct eth_device *dev;
struct phy_device *phydev; struct phy_device *phydev;
void __iomem *iobase;
}; };
struct sh_eth_dev { struct sh_eth_dev {
@ -601,7 +602,7 @@ enum FIFO_SIZE_BIT {
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
}; };
static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
int enum_index) int enum_index)
{ {
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
@ -611,17 +612,17 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
#else #else
#error #error
#endif #endif
return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; return (unsigned long)port->iobase + reg_offset[enum_index];
} }
static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
int enum_index) int enum_index)
{ {
outl(data, sh_eth_reg_addr(eth, enum_index)); outl(data, sh_eth_reg_addr(port, enum_index));
} }
static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, static inline unsigned long sh_eth_read(struct sh_eth_info *port,
int enum_index) int enum_index)
{ {
return inl(sh_eth_reg_addr(eth, enum_index)); return inl(sh_eth_reg_addr(port, enum_index));
} }