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fpga: zynqmp: Modify PL bitstream loading sequence

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This patch modifies PL bitstream loading sequence as per
latest Xilfpga which supports all variants of bitstream images
generated from vivado and from bootgen. With this new change in
Xilfpga, uboot doesn't need to validate and swap bitstream as it will
be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting
PMUFW version before skipping the validation and swap sequence as there
can be old PMUFW which doesn't supports this feature. In this case, driver
uses old way of PL bitstream loading sequence.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu
2018-08-21 15:44:50 +05:30
committed by Michal Simek
parent b94a8271cc
commit fbf7fb0f9f
2 changed files with 26 additions and 9 deletions
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2
arch/arm/include/asm/arch-zynqmp/sys_proto.h
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@@ -34,6 +34,8 @@
#define ZYNQMP_PM_VERSION_INVALID ~0
#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
enum {
IDCODE,
VERSION,