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arm: dts: rk3399: Sync roc-pc-mezzanine from v5.7-rc1

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Sync Firefly ROC-RK3399-PC Mezzanine Board dts file
from Linux v5.7-rc1.

Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
2020-04-28 15:30:18 +05:30
committed by Kever Yang
parent 167efc2c7a
commit fb3f5cdbf1
2 changed files with 94 additions and 0 deletions
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1
arch/arm/dts/Makefile
View File

@@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \ rk3399-puma-ddr1866.dtb \
rk3399-roc-pc.dtb \ rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4.dtb \ rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \ rk3399-rock960.dtb \
rk3399-rockpro64.dtb rk3399-rockpro64.dtb

93
arch/arm/dts/rk3399-roc-pc-mezzanine.dts Normal file
View File

@@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
* Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
*/
/dts-v1/;
#include "rk3399-roc-pc.dtsi"
/ {
model = "Firefly ROC-RK3399-PC Mezzanine Board";
compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
vcc3v3_ngff: vcc3v3-ngff {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_ngff";
enable-active-high;
gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_ngff_en>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc3v3_pcie: vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie3v3-supply = <&vcc3v3_pcie>;
vpcie1v8-supply = <&vcc1v8_pmu>;
vpcie0v9-supply = <&vcca_0v9>;
status = "okay";
};
&pinctrl {
ngff {
vcc3v3_ngff_en: vcc3v3-ngff-en {
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
vcc3v3_pcie_en: vcc3v3-pcie-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_perst: pcie-perst {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_ngff>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};