Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"
This reverts commit 1e6ebee667
.
It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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@ -402,15 +402,6 @@ config FSP_BROKEN_HOB
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do not overwrite the important boot service data which is used by
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FSP, otherwise the subsequent call to fsp_notify() will fail.
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config FSP_LOCKDOWN_SPI
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bool
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depends on HAVE_FSP
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help
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Some Intel FSP (like Braswell) does SPI lock-down during the call
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to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
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for such FSP and U-Boot will configure the SPI opcode registers
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before the lock-down.
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config ENABLE_MRC_CACHE
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bool "Enable MRC cache"
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depends on !EFI && !SYS_COREBOOT
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@ -19,8 +19,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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extern void ich_spi_config_opcode(struct udevice *dev);
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int checkcpu(void)
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{
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return 0;
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@ -51,28 +49,6 @@ void board_final_cleanup(void)
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{
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u32 status;
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#ifdef CONFIG_FSP_LOCKDOWN_SPI
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struct udevice *dev;
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/*
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* Some Intel FSP (like Braswell) does SPI lock-down during the call
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* to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
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* it's bootloader's responsibility to configure the SPI controller's
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* opcode registers properly otherwise SPI controller driver doesn't
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* know how to communicate with the SPI flash device.
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*
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* Note we cannot do such configuration elsewhere (eg: during the SPI
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* controller driver's probe() routine), because:
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*
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* 1). U-Boot SPI controller driver does not set the lock-down bit
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* 2). Any SPI transfer will corrupt the contents of these registers
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*
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* Hence we have to do it right here before SPI lock-down bit is set.
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*/
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if (!uclass_first_device_err(UCLASS_SPI, &dev))
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ich_spi_config_opcode(dev);
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#endif
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/* call into FspNotify */
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debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
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status = fsp_notify(NULL, INIT_PHASE_BOOT);
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