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Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

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This commit is contained in:
Tom Rini
2013-11-25 10:42:13 -05:00
parent 5a4fe1aaf1 2c17e6d1d9
commit faca8ff55f
39 changed files with 532 additions and 220 deletions
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1
arch/arm/cpu/armv7/am33xx/Makefile
View File

@@ -19,4 +19,3 @@ obj-y += ddr.o
obj-y += emif4.o
obj-y += board.o
obj-y += mux.o
obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o

196
arch/arm/cpu/armv7/am33xx/elm.c
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@@ -1,196 +0,0 @@
/*
* (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* BCH Error Location Module (ELM) support.
*
* NOTE:
* 1. Supports only continuous mode. Dont see need for page mode in uboot
* 2. Supports only syndrome polynomial 0. i.e. poly local variable is
* always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
* sets in uboot
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/cpu.h>
#include <asm/omap_gpmc.h>
#include <asm/arch/elm.h>
#define ELM_DEFAULT_POLY (0)
struct elm *elm_cfg;
/**
* elm_load_syndromes - Load BCH syndromes based on nibble selection
* @syndrome: BCH syndrome
* @nibbles:
* @poly: Syndrome Polynomial set to use
*
* Load BCH syndromes based on nibble selection
*/
static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
{
u32 *ptr;
u32 val;
/* reg 0 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
(syndrome[3] << 24);
writel(val, ptr);
/* reg 1 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
(syndrome[7] << 24);
writel(val, ptr);
/* BCH 8-bit with 26 nibbles (4*8=32) */
if (nibbles > 13) {
/* reg 2 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
(syndrome[11] << 24);
writel(val, ptr);
/* reg 3 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
val = syndrome[12] | (syndrome[13] << 8) |
(syndrome[14] << 16) | (syndrome[15] << 24);
writel(val, ptr);
}
/* BCH 16-bit with 52 nibbles (7*8=56) */
if (nibbles > 26) {
/* reg 4 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
val = syndrome[16] | (syndrome[17] << 8) |
(syndrome[18] << 16) | (syndrome[19] << 24);
writel(val, ptr);
/* reg 5 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
val = syndrome[20] | (syndrome[21] << 8) |
(syndrome[22] << 16) | (syndrome[23] << 24);
writel(val, ptr);
/* reg 6 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
val = syndrome[24] | (syndrome[25] << 8) |
(syndrome[26] << 16) | (syndrome[27] << 24);
writel(val, ptr);
}
}
/**
* elm_check_errors - Check for BCH errors and return error locations
* @syndrome: BCH syndrome
* @nibbles:
* @error_count: Returns number of errrors in the syndrome
* @error_locations: Returns error locations (in decimal) in this array
*
* Check the provided syndrome for BCH errors and return error count
* and locations in the array passed. Returns -1 if error is not correctable,
* else returns 0
*/
int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
u32 *error_locations)
{
u8 poly = ELM_DEFAULT_POLY;
s8 i;
u32 location_status;
elm_load_syndromes(syndrome, nibbles, poly);
/* start processing */
writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
| ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
/* wait for processing to complete */
while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
;
/* clear status */
writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
&elm_cfg->irqstatus);
/* check if correctable */
location_status = readl(&elm_cfg->error_location[poly].location_status);
if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
return -1;
/* get error count */
*error_count = readl(&elm_cfg->error_location[poly].location_status) &
ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
for (i = 0; i < *error_count; i++) {
error_locations[i] =
readl(&elm_cfg->error_location[poly].error_location_x[i]);
}
return 0;
}
/**
* elm_config - Configure ELM module
* @level: 4 / 8 / 16 bit BCH
*
* Configure ELM module based on BCH level.
* Set mode as continuous mode.
* Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
* Also, the mode is set only for syndrome 0
*/
int elm_config(enum bch_level level)
{
u32 val;
u8 poly = ELM_DEFAULT_POLY;
u32 buffer_size = 0x7FF;
/* config size and level */
val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
writel(val, &elm_cfg->location_config);
/* config continous mode */
/* enable interrupt generation for syndrome polynomial set */
writel((readl(&elm_cfg->irqenable) | (0x1 << poly)),
&elm_cfg->irqenable);
/* set continuous mode for the syndrome polynomial set */
writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)),
&elm_cfg->page_ctrl);
return 0;
}
/**
* elm_reset - Do a soft reset of ELM
*
* Perform a soft reset of ELM and return after reset is done.
*/
void elm_reset(void)
{
/* initiate reset */
writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
&elm_cfg->sysconfig);
/* wait for reset complete and normal operation */
while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
ELM_SYSSTATUS_RESETDONE)
;
}
/**
* elm_init - Initialize ELM module
*
* Initialize ELM support. Currently it does only base address init
* and ELM reset.
*/
void elm_init(void)
{
elm_cfg = (struct elm *)ELM_BASE;
elm_reset();
}

52
arch/arm/cpu/armv7/am33xx/mem.c
View File

@@ -22,17 +22,6 @@
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
#endif
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
@@ -61,11 +50,34 @@ void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
#ifdef CONFIG_CMD_NAND
const u32 *gpmc_config = NULL;
u32 base = 0;
#if defined(CONFIG_NOR)
/* configure GPMC for NOR */
const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
STNOR_GPMC_CONFIG2,
STNOR_GPMC_CONFIG3,
STNOR_GPMC_CONFIG4,
STNOR_GPMC_CONFIG5,
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
#elif defined(CONFIG_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6,
0
};
u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
u32 base = 0;
#endif
/* global settings */
writel(0x00000008, &gpmc_cfg->sysconfig);
@@ -81,12 +93,6 @@ void gpmc_init(void)
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
#ifdef CONFIG_CMD_NAND
gpmc_config = gpmc_m_nand;
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#endif
/* enable chip-select specific configurations */
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
}

5
arch/arm/include/asm/arch-am33xx/mem.h
View File

@@ -68,9 +68,4 @@
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
/* make it readable for the gpmc_init */
#define PISMO1_NOR_BASE FLASH_BASE
#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
#define PISMO1_NAND_SIZE GPMC_SIZE_256M
#endif /* endif _MEM_H_ */

0
arch/arm/include/asm/arch-am33xx/elm.h → arch/arm/include/asm/omap_elm.h
View File

16
arch/arm/include/asm/omap_gpmc.h
View File

@@ -68,4 +68,20 @@
}
#endif
enum omap_ecc {
/* 1-bit ECC calculation by Software, Error detection by Software */
OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
/* 1-bit ECC calculation by GPMC, Error detection by Software */
/* ECC layout compatible to legacy ROMCODE. */
OMAP_ECC_HAM1_CODE_HW,
/* 4-bit ECC calculation by GPMC, Error detection by Software */
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
/* 4-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH4_CODE_HW,
/* 8-bit ECC calculation by GPMC, Error detection by Software */
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH8_CODE_HW,
};
#endif /* __ASM_OMAP_GPMC_H */

24
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
View File

@@ -33,6 +33,9 @@ void init_early_memctl_regs(void)
#ifndef CONFIG_A003399_NOR_WORKAROUND
#ifdef CONFIG_SYS_CSPR0_EXT
set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
#endif
#ifdef CONFIG_SYS_CSOR0_EXT
set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
#endif
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
@@ -43,6 +46,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR1_EXT
set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
#endif
#ifdef CONFIG_SYS_CSOR1_EXT
set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
#endif
#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
@@ -57,6 +63,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR2_EXT
set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
#endif
#ifdef CONFIG_SYS_CSOR2_EXT
set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
#endif
#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
@@ -71,6 +80,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR3_EXT
set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
#endif
#ifdef CONFIG_SYS_CSOR3_EXT
set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
#endif
#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
@@ -85,6 +97,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR4_EXT
set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
#endif
#ifdef CONFIG_SYS_CSOR4_EXT
set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
#endif
#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
@@ -99,6 +114,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR5_EXT
set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
#endif
#ifdef CONFIG_SYS_CSOR5_EXT
set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
#endif
#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
@@ -113,6 +131,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR6_EXT
set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
#endif
#ifdef CONFIG_SYS_CSOR6_EXT
set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
#endif
#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
@@ -127,6 +148,9 @@ void init_early_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR7_EXT
set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
#endif
#ifdef CONFIG_SYS_CSOR7_EXT
set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
#endif
#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);

2
arch/powerpc/include/asm/fsl_ifc.h
View File

@@ -77,6 +77,7 @@
#define CSOR_NAND_PGS_512 0x00000000
#define CSOR_NAND_PGS_2K 0x00080000
#define CSOR_NAND_PGS_4K 0x00100000
#define CSOR_NAND_PGS_8K 0x00180000
/* Spare region Size */
#define CSOR_NAND_SPRZ_MASK 0x0000E000
#define CSOR_NAND_SPRZ_SHIFT 13
@@ -86,6 +87,7 @@
#define CSOR_NAND_SPRZ_210 0x00006000
#define CSOR_NAND_SPRZ_218 0x00008000
#define CSOR_NAND_SPRZ_224 0x0000A000
#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
/* Pages Per Block */
#define CSOR_NAND_PB_MASK 0x00000700
#define CSOR_NAND_PB_SHIFT 8