arm: add support to corstone1000 platform
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. This code adds the support for the Cortex-A35 implementation at host side, it contains also the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the FPGA MPS3 board implementation of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Rui Miguel Silva
Tom Rini
parent
bfef72e4dd
commit
f98457d70a
@ -1352,6 +1352,12 @@ config ARCH_VEXPRESS64
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select ENV_IS_IN_FLASH if MTD
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imply DISTRO_DEFAULTS
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config TARGET_CORSTONE1000
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bool "Support Corstone1000 Platform"
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select ARM64
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select PL01X_SERIAL
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select DM
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config TARGET_TOTAL_COMPUTE
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bool "Support Total Compute Platform"
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select ARM64
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@ -2300,7 +2306,7 @@ source "arch/arm/mach-nexell/Kconfig"
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source "arch/arm/mach-npcm/Kconfig"
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source "board/armltd/total_compute/Kconfig"
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source "board/armltd/corstone1000/Kconfig"
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source "board/bosch/shc/Kconfig"
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source "board/bosch/guardian/Kconfig"
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source "board/Marvell/octeontx/Kconfig"
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@ -1273,6 +1273,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
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dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
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dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
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corstone1000-fvp.dtb
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include $(srctree)/scripts/Makefile.dts
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targets += $(dtb-y)
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51
arch/arm/dts/corstone1000-fvp.dts
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51
arch/arm/dts/corstone1000-fvp.dts
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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/dts-v1/;
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#include "corstone1000.dtsi"
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/ {
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model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
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compatible = "arm,corstone1000-fvp";
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smsc: ethernet@4010000 {
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compatible = "smsc,lan91c111";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <2>;
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};
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vmmc_v3_3d: fixed_v3_3d {
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compatible = "regulator-fixed";
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regulator-name = "vmmc_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sdmmc0: mmc@40300000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x40300000 0x1000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <12000000>;
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vmmc-supply = <&vmmc_v3_3d>;
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clocks = <&smbclk>, <&refclk100mhz>;
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clock-names = "smclk", "apb_pclk";
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};
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sdmmc1: mmc@50000000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x50000000 0x10000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <12000000>;
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vmmc-supply = <&vmmc_v3_3d>;
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clocks = <&smbclk>, <&refclk100mhz>;
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clock-names = "smclk", "apb_pclk";
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};
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};
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32
arch/arm/dts/corstone1000-mps3.dts
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32
arch/arm/dts/corstone1000-mps3.dts
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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/dts-v1/;
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#include "corstone1000.dtsi"
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/ {
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model = "ARM Corstone1000 FPGA MPS3 board";
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compatible = "arm,corstone1000-mps3";
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smsc: ethernet@4010000 {
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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};
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usb_host: usb@40200000 {
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compatible = "nxp,usb-isp1763";
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reg = <0x40200000 0x100000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <16>;
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dr_mode = "host";
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};
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};
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164
arch/arm/dts/corstone1000.dtsi
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164
arch/arm/dts/corstone1000.dtsi
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@ -0,0 +1,164 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0>;
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next-level-cache = <&L2_0>;
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};
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};
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memory@88200000 {
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device_type = "memory";
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reg = <0x88200000 0x77e00000>;
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};
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gic: interrupt-controller@1c000000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1c010000 0x1000>,
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<0x1c02f000 0x2000>,
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<0x1c04f000 0x1000>,
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<0x1c06f000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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smbclk: refclk24mhzx2 {
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/* Reference 24MHz clock x 2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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uartclk: uartclk {
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/* UART clock - 50MHz */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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timer@1a220000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x1a220000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-frequency = <50000000>;
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ranges;
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frame@1a230000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1a230000 0x1000>;
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};
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};
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uart0: serial@1a510000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a510000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: serial@1a520000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a520000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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mhu_hse1: mailbox@1b820000 {
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compatible = "arm,mhuv2-tx", "arm,primecell";
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reg = <0x1b820000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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arm,mhuv2-protocols = <0 0>;
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secure-status = "okay"; /* secure-world-only */
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status = "disabled";
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};
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mhu_seh1: mailbox@1b830000 {
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compatible = "arm,mhuv2-rx", "arm,primecell";
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reg = <0x1b830000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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arm,mhuv2-protocols = <0 0>;
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secure-status = "okay"; /* secure-world-only */
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status = "disabled";
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};
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};
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};
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12
board/armltd/corstone1000/Kconfig
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12
board/armltd/corstone1000/Kconfig
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@ -0,0 +1,12 @@
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if TARGET_CORSTONE1000
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config SYS_BOARD
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default "corstone1000"
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config SYS_VENDOR
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default "armltd"
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config SYS_CONFIG_NAME
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default "corstone1000"
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endif
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7
board/armltd/corstone1000/MAINTAINERS
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7
board/armltd/corstone1000/MAINTAINERS
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@ -0,0 +1,7 @@
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CORSTONE1000 BOARD
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M: Rui Miguel Silva <rui.silva@linaro.org>
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M: Vishnu Banavath <vishnu.banavath@arm.com>
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S: Maintained
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F: board/armltd/corstone1000/
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F: include/configs/corstone1000.h
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F: configs/corstone1000_defconfig
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7
board/armltd/corstone1000/Makefile
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7
board/armltd/corstone1000/Makefile
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Arm Limited
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# (C) Copyright 2022 Linaro
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# Rui Miguel Silva <rui.silva@linaro.org>
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obj-y := corstone1000.o
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91
board/armltd/corstone1000/corstone1000.c
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91
board/armltd/corstone1000/corstone1000.c
Normal file
@ -0,0 +1,91 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022 ARM Limited
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* (C) Copyright 2022 Linaro
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* Rui Miguel Silva <rui.silva@linaro.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <netdev.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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static struct mm_region corstone1000_mem_map[] = {
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{
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/* CVM */
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.virt = 0x02000000UL,
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.phys = 0x02000000UL,
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.size = 0x02000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* QSPI */
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.virt = 0x08000000UL,
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.phys = 0x08000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Host Peripherals */
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.virt = 0x1A000000UL,
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.phys = 0x1A000000UL,
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.size = 0x26000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* USB */
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.virt = 0x40200000UL,
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.phys = 0x40200000UL,
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.size = 0x00100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* ethernet */
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.virt = 0x40100000UL,
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.phys = 0x40100000UL,
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.size = 0x00100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* OCVM */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = corstone1000_mem_map;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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52
configs/corstone1000_defconfig
Normal file
52
configs/corstone1000_defconfig
Normal file
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_TARGET_CORSTONE1000=y
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CONFIG_SYS_TEXT_BASE=0x80000000
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3"
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CONFIG_IDENT_STRING=" corstone1000 aarch64 "
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CONFIG_SYS_LOAD_ADDR=0x82100000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
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CONFIG_BOOTCOMMAND="run retrieve_kernel_load_addr; echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
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CONFIG_CONSOLE_RECORD=y
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CONFIG_LOGLEVEL=7
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_SYS_PROMPT="corstone1000# "
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CONFIG_SYS_MAXARGS=64
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CONFIG_SYS_CBSIZE=512
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# CONFIG_CMD_CONSOLE is not set
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_XIMG is not set
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CONFIG_CMD_LOADM=y
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# CONFIG_CMD_LOADS is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_EMULATION=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
41
include/configs/corstone1000.h
Normal file
41
include/configs/corstone1000.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2022 ARM Limited
|
||||
* (C) Copyright 2022 Linaro
|
||||
* Rui Miguel Silva <rui.silva@linaro.org>
|
||||
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
|
||||
*
|
||||
* Configuration for Corstone1000. Parts were derived from other ARM
|
||||
* configurations.
|
||||
*/
|
||||
|
||||
#ifndef __CORSTONE1000_H
|
||||
#define __CORSTONE1000_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define V2M_BASE 0x80000000
|
||||
|
||||
#define CONFIG_PL011_CLOCK 50000000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM_1 (V2M_BASE)
|
||||
#define PHYS_SDRAM_1_SIZE 0x80000000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"usb_pgood_delay=250\0" \
|
||||
"boot_bank_flag=0x08002000\0" \
|
||||
"kernel_addr_bank_0=0x083EE000\0" \
|
||||
"kernel_addr_bank_1=0x0936E000\0" \
|
||||
"retrieve_kernel_load_addr=" \
|
||||
"if itest.l *${boot_bank_flag} == 0; then " \
|
||||
"setenv kernel_addr $kernel_addr_bank_0;" \
|
||||
"else " \
|
||||
"setenv kernel_addr $kernel_addr_bank_1;" \
|
||||
"fi;" \
|
||||
"\0" \
|
||||
"kernel_addr_r=0x88200000\0"
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user