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powerpc/p2041: fix serdes reference clock frequency display for PC board

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PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Shaohui Xie 2013-03-25 07:40:18 +00:00 committed by Andy Fleming
parent 0fecbba80a
commit f9539a9caa
1 changed files with 11 additions and 0 deletions
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11
board/freescale/p2041rdb/p2041rdb.c
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@ -227,6 +227,17 @@ int misc_init_r(void)
"'00' is unsupported\n");
else
actual[i] = freq[i][clock];
/*
* PC board uses a different CPLD with PB board, this CPLD
* has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
* board has cpld_ver_sub = 0, and pcba_ver = 4.
*/
if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
(CPLD_READ(pcba_ver) == 5)) {
/* PC board bank2 frequency */
actual[i] = freq[i-1][clock];
}
}
for (i = 0; i < NUM_SRDS_BANKS; i++) {