mpc85xx: Add board support for the eXMeritus HWW-1U-1A devices
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones. Two independent P2020 computers may
be found inside each zone. Complete hardware support is included.
High-level hardware overview:
* DO-160 certified for passenger aircraft (noncritical)
* TEMPEST ceritified for RED/BLACK separation
* 3 zones per chassis, 2 computers per zone (total of 6)
* Dual-core 1.066GHz P2020 per computer
* One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
* Removable 80GB or 160GB Intel X18-M SSD per computer
* Front-accessible dual-port E1000E per computer
* Front-accessible serial console per computer
* Front-accessible USB port per computer
* Internal Gigabit crossover within each TEMPEST zone
* Internal unidirectional fiber links across TEMPEST zones
* Battery-backed DS1339 I2C RTC on each CPU.
Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.
Additional notes:
* SPD detection is only known to work with the DO-160-certified DIMMs
* CPU reset is a little quirky due to hardware misfeature. Proper
support for the hardware reset mechanism has been left for a later
patch series to address.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kyle Moffett
Kumar Gala
parent
c4eba6ec5c
commit
f8bbb4dad0
@ -321,6 +321,10 @@ Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
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TOP5200 MPC5200
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TOP9000 ARM926EJS (AT91SAM9xxx SoC)
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Kyle Moffett <Kyle.D.Moffett@boeing.com>
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HWW1U1A P2020
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Tolunay Orkun <torkun@nextio.com>
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csb272 PPC405GP
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48
board/exmeritus/hww1u1a/Makefile
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48
board/exmeritus/hww1u1a/Makefile
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@ -0,0 +1,48 @@
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#
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# Copyright 2007-2009 Freescale Semiconductor, Inc.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-$(CONFIG_DDR_SPD) += ddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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34
board/exmeritus/hww1u1a/ddr.c
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34
board/exmeritus/hww1u1a/ddr.c
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@ -0,0 +1,34 @@
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/*
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* Copyright 2009-2010 eXMeritus, A Boeing Company
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* We only support one DIMM, so according to the P2020 docs we should
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* set the options as follows:
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*/
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popts->cs_local_opts[0].odt_rd_cfg = 0;
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popts->cs_local_opts[0].odt_wr_cfg = 4;
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popts->cs_local_opts[1].odt_rd_cfg = 0;
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popts->cs_local_opts[1].odt_wr_cfg = 0;
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popts->half_strength_driver_enable = 0;
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/* Manually configured for our static clock rate */
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popts->clk_adjust = 4;
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popts->cpo_override = 4;
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popts->write_data_delay = 2;
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popts->twoT_en = 0;
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}
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69
board/exmeritus/hww1u1a/gpios.h
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69
board/exmeritus/hww1u1a/gpios.h
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@ -0,0 +1,69 @@
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/*
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* Copyright 2010 eXMeritus, A Boeing Company
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/mpc85xx_gpio.h>
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/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
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#define GPIO_CPU_ID (1UL << (31 - 8))
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#define GPIO_BLUE_LED (1UL << (31 - 9))
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#define GPIO_DIMM_RESET (1UL << (31 - 10))
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#define GPIO_USB_RESET (1UL << (31 - 11))
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#define GPIO_UNUSED_12 (1UL << (31 - 12))
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#define GPIO_GETH0_RESET (1UL << (31 - 13))
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#define GPIO_RS422_RE (1UL << (31 - 14))
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#define GPIO_RS422_DE (1UL << (31 - 15))
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#define IRQ_I2CINT (1UL << (31 - 20))
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#define IRQ_FANINT (1UL << (31 - 21))
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#define IRQ_DIMM_EVENT (1UL << (31 - 22))
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#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
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/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
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#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0))
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#define GPIO_CPUA_CPU_READY (1UL << (31 - 1))
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#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2))
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#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3))
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#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */
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#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */
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#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */
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#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */
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#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16))
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#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17))
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#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18))
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#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19))
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/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
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#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0))
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#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1))
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#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2))
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#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3))
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#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4))
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#define GPIO_CPUB_CPU_READY (1UL << (31 - 5))
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#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6))
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#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7))
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#define IRQ_CPUB_SD_1A (1UL << (31 - 16))
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#define IRQ_CPUB_SD_2B (1UL << (31 - 17))
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#define IRQ_CPUB_SD_2A (1UL << (31 - 18))
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#define IRQ_CPUB_SD_1B (1UL << (31 - 19))
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/* If it isn't CPU A then it's CPU B */
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static inline unsigned int hww1u1a_is_cpu_a(void)
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{
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return !mpc85xx_gpio_get(GPIO_CPU_ID);
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}
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277
board/exmeritus/hww1u1a/hww1u1a.c
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277
board/exmeritus/hww1u1a/hww1u1a.c
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@ -0,0 +1,277 @@
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/*
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* Copyright 2009-2011 eXMeritus, A Boeing Company
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* Copyright 2007-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <linux/ctype.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <i2c.h>
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#include <pca953x.h>
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#include "gpios.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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unsigned int gpio_high = 0;
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unsigned int gpio_low = 0;
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unsigned int gpio_in = 0;
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unsigned int i;
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puts("Board: HWW-1U-1A ");
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/*
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* First just figure out which CPU we're on, then use that to
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* configure the lists of other GPIOs to be programmed.
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*/
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mpc85xx_gpio_set_in(GPIO_CPU_ID);
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if (hww1u1a_is_cpu_a()) {
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puts("CPU A\n");
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/* We want to turn on some LEDs */
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gpio_high |= GPIO_CPUA_CPU_READY;
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gpio_low |= GPIO_CPUA_DEBUG_LED1;
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gpio_low |= GPIO_CPUA_DEBUG_LED2;
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/* Disable the unused transmitters */
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gpio_low |= GPIO_CPUA_TDIS1A;
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gpio_high |= GPIO_CPUA_TDIS1B;
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gpio_low |= GPIO_CPUA_TDIS2A;
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gpio_high |= GPIO_CPUA_TDIS2B;
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} else {
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puts("CPU B\n");
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/* We want to turn on some LEDs */
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gpio_high |= GPIO_CPUB_CPU_READY;
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gpio_low |= GPIO_CPUB_DEBUG_LED1;
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gpio_low |= GPIO_CPUB_DEBUG_LED2;
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/* Enable the appropriate receivers */
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gpio_high |= GPIO_CPUB_RMUX_SEL0A;
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gpio_high |= GPIO_CPUB_RMUX_SEL0B;
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gpio_low |= GPIO_CPUB_RMUX_SEL1A;
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gpio_low |= GPIO_CPUB_RMUX_SEL1B;
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}
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/* These GPIOs are common */
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gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT;
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gpio_low |= GPIO_RS422_RE;
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gpio_high |= GPIO_RS422_DE;
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/* Ok, now go ahead and program all of those in one go */
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mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in,
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gpio_high|gpio_low,
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gpio_high);
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/*
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* If things have been taken out of reset early (for example, by one
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* of the BDI3000 debuggers), then we need to put them back in reset
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* and delay a while before we continue.
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*/
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if (mpc85xx_gpio_get(GPIO_RESETS)) {
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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puts("Debugger detected... extra device reset enabled!\n");
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/* Put stuff into reset and disable the DDR controller */
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mpc85xx_gpio_set_low(GPIO_RESETS);
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out_be32(&ddr->sdram_cfg, 0x00000000);
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puts(" Waiting 1 sec for reset...");
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for (i = 0; i < 10; i++) {
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udelay(100000);
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puts(".");
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}
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puts("\n");
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}
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/* Now bring everything back out of reset again */
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mpc85xx_gpio_set_high(GPIO_RESETS);
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return 0;
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}
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/*
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* This little shell function just returns whether or not it's CPU A.
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* It can be used to select the right device-tree when booting, etc.
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*/
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int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag,
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int argc, char * const argv[])
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{
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if (argc > 1)
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cmd_usage(cmdtp);
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if (hww1u1a_is_cpu_a())
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return 0;
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else
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return 1;
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}
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U_BOOT_CMD(
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test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a,
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"Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board",
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""
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);
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/* Create a prompt-like string: "uboot@HOSTNAME% " */
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#define PROMPT_PREFIX "uboot@exm"
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#define PROMPT_SUFFIX "% "
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/* This function returns a PS1 prompt based on the serial number */
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static char *hww1u1a_prompt;
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const char *hww1u1a_get_ps1(void)
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{
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unsigned long len, i, j;
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const char *serialnr;
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/* If our prompt was already set, just use that */
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if (hww1u1a_prompt)
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return hww1u1a_prompt;
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/* Use our serial number if present, otherwise a default */
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serialnr = getenv("serial#");
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if (!serialnr || !serialnr[0])
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serialnr = "999999-X";
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/*
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* We will turn the serial number into a hostname by:
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* (A) Delete all non-alphanumerics.
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* (B) Lowercase all letters.
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* (C) Prefix "exm".
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* (D) Suffix "a" for CPU A and "b" for CPU B.
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*/
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for (i = 0, len = 0; serialnr[i]; i++) {
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if (isalnum(serialnr[i]))
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len++;
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}
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len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */
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hww1u1a_prompt = malloc(len);
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if (!hww1u1a_prompt)
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return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX;
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/* Now actually fill it in */
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i = 0;
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/* Handle the prefix */
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for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++)
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hww1u1a_prompt[i++] = PROMPT_PREFIX[j];
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/* Now the serial# part of the hostname */
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for (j = 0; serialnr[j]; j++)
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if (isalnum(serialnr[j]))
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hww1u1a_prompt[i++] = tolower(serialnr[j]);
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/* Now the CPU id ("a" or "b") */
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hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b';
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/* Finally the suffix */
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for (j = 0; j < sizeof(PROMPT_SUFFIX); j++)
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hww1u1a_prompt[i++] = PROMPT_SUFFIX[j];
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/* This should all have added up, but just in case */
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hww1u1a_prompt[len - 1] = '\0';
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/* Now we're done */
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return hww1u1a_prompt;
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}
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap bootflash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for FLASH */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct tsec_info_struct tsec_info[4];
|
||||
struct fsl_pq_mdio_info mdio_info;
|
||||
|
||||
SET_STD_TSEC_INFO(tsec_info[0], 1);
|
||||
SET_STD_TSEC_INFO(tsec_info[1], 2);
|
||||
SET_STD_TSEC_INFO(tsec_info[2], 3);
|
||||
|
||||
if (hww1u1a_is_cpu_a())
|
||||
tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA;
|
||||
else
|
||||
tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB;
|
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
|
||||
mdio_info.name = DEFAULT_MII_NAME;
|
||||
fsl_pq_mdio_init(bis, &mdio_info);
|
||||
|
||||
tsec_eth_init(bis, tsec_info, 3);
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
FT_FSL_PCI_SETUP;
|
||||
}
|
||||
34
board/exmeritus/hww1u1a/law.c
Normal file
34
board/exmeritus/hww1u1a/law.c
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
106
board/exmeritus/hww1u1a/tlb.c
Normal file
106
board/exmeritus/hww1u1a/tlb.c
Normal file
@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Copyright 2009-2010 eXMeritus, A Boeing Company
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Boot page */
|
||||
SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR,
|
||||
CONFIG_BPTR_VIRT_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR,
|
||||
CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/*
|
||||
* W**G* - FLASH (Will be *I*G* after relocation to RAM)
|
||||
*
|
||||
* This maps both SPI FLASH chips (128MByte per chip)
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* *I*G* - PCI memory
|
||||
*
|
||||
* We have 1.5GB total PCI-E memory space to map and we want to use
|
||||
* the minimum possible number of TLB entries. Since Book-E TLB
|
||||
* entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* *I*G* - PCI I/O
|
||||
*
|
||||
* This one entry covers all 3 64k PCI-E I/O windows
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT,
|
||||
CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -599,6 +599,7 @@ sbc8560 powerpc mpc85xx sbc8560 -
|
||||
sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560
|
||||
sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560
|
||||
socrates powerpc mpc85xx socrates
|
||||
HWW1U1A powerpc mpc85xx hww1u1a exmeritus
|
||||
MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
|
||||
MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT
|
||||
MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND
|
||||
|
||||
451
include/configs/HWW1U1A.h
Normal file
451
include/configs/HWW1U1A.h
Normal file
@ -0,0 +1,451 @@
|
||||
/*
|
||||
* Copyright 2009-2010 eXMeritus, A Boeing Company
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* HardwareWall HWW-1U-1A airborne unit configuration file
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High-level system configuration options */
|
||||
#define CONFIG_BOOKE /* Power/PowerPC Book-E */
|
||||
#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */
|
||||
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */
|
||||
#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */
|
||||
#define CONFIG_FSL_LAW /* FreeScale Local Access Window */
|
||||
#define CONFIG_P2020 /* FreeScale P2020 */
|
||||
#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */
|
||||
#define CONFIG_MP /* Multiprocessing support */
|
||||
#define CONFIG_HWCONFIG /* Use hwconfig from environment */
|
||||
|
||||
#define CONFIG_L2_CACHE /* L2 cache enabled */
|
||||
#define CONFIG_BTB /* Branch predition enabled */
|
||||
|
||||
#define CONFIG_PANIC_HANG /* No board reset on panic */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */
|
||||
#define CONFIG_CMD_REGINFO /* Dump various CPU regs */
|
||||
|
||||
/*
|
||||
* Allow the use of 36-bit physical addresses. Device-trees with 64-bit
|
||||
* addresses have known compatibility issues with some existing kernels.
|
||||
*/
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
|
||||
|
||||
/* Reserve plenty of RAM for malloc (we have 2GB+) */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
|
||||
/* How much L2 cache do we map so we can use it as RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
/* This is our temporary global data area just above the stack */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* The stack grows down from the global data area */
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* Enable IRQs and watchdog with a 1000Hz system decrementer */
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Clock crystal configuration:
|
||||
* (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
|
||||
* (2) CCB: Multiplier from SYS_CLK
|
||||
* (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
|
||||
*/
|
||||
#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
|
||||
#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM
|
||||
* 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1
|
||||
* 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused)
|
||||
* 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3
|
||||
* 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH
|
||||
* 0xe800_0000 0xefff_ffff 128M Spansion FLASH
|
||||
* 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0)
|
||||
* 0xffe0_0000 0xffef_ffff 1M CCSR
|
||||
* 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller
|
||||
*/
|
||||
|
||||
/* Virtual Memory Map */
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */
|
||||
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */
|
||||
|
||||
/*
|
||||
* U-Boot Environment Image: The two sectors immediately below U-Boot
|
||||
* form the U-Boot environment (regular and redundant).
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */
|
||||
#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* Only use 8kB of each environment sector for data */
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8kB */
|
||||
#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* Serial Console Configuration */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/* Echo back characters received during a serial download */
|
||||
#define CONFIG_LOADS_ECHO
|
||||
|
||||
/* Allow a serial-download to temporarily change baud */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* PCI and PCI-Express Support */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI_PNP /* Scan PCI busses */
|
||||
#define CONFIG_CMD_PCI /* Enable the "pci" command */
|
||||
#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */
|
||||
#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */
|
||||
|
||||
/* Enable 2 of the 3 PCI-E controllers */
|
||||
#define CONFIG_PCIE3
|
||||
#undef CONFIG_PCIE2
|
||||
#define CONFIG_PCIE1
|
||||
|
||||
/* Display human-readable names when initializing */
|
||||
#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
|
||||
#define CONFIG_SYS_PCIE2_NAME "Unused"
|
||||
#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
|
||||
|
||||
/*
|
||||
* PCI bus addresses
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* Generic FreeScale hardware I2C support */
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C bus configuration */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x51
|
||||
|
||||
/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
/* Turn off RTC square-wave output to save battery */
|
||||
#define CONFIG_SYS_RTC_DS1337_NOOSC
|
||||
|
||||
/* PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554) */
|
||||
#define CONFIG_PCA953X
|
||||
#define CONFIG_CMD_PCA953X
|
||||
#define CONFIG_CMD_PCA953X_INFO
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* FreeScale DDR2/3 SDRAM Controller */
|
||||
#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */
|
||||
#define CONFIG_DDR_ECC /* Enable ECC by default */
|
||||
#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */
|
||||
#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */
|
||||
#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
/* Standard P2020 DDR controller parameters */
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
|
||||
/* Make sure to tell the DDR controller to preinitialze all of RAM */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
|
||||
|
||||
/* Flash banks (2x 128MB) */
|
||||
#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
|
||||
#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
|
||||
|
||||
/*
|
||||
* Flash access modes and timings (values are the defaults after a RESET).
|
||||
*
|
||||
* NOTE: These could probably be optimized but are more than sufficient for
|
||||
* this particular system for the moment.
|
||||
*/
|
||||
#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
|
||||
#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
|
||||
|
||||
/* Configure both flash banks */
|
||||
#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
|
||||
#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
|
||||
#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
|
||||
#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
|
||||
|
||||
/* Flash timeouts (in ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */
|
||||
|
||||
/* Quiet flash testing */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
|
||||
/* Make program/erase count down from 45/5 (9....8....7....) */
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* Ethernet Device Support */
|
||||
#define CONFIG_MII /* Enable MII PHY code */
|
||||
#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */
|
||||
#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */
|
||||
#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */
|
||||
|
||||
/* Turn on various helpful networking commands */
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
|
||||
#define CONFIG_TSEC_ENET
|
||||
#define CONFIG_TSEC1
|
||||
#define CONFIG_TSEC2
|
||||
#define CONFIG_TSEC3
|
||||
#define CONFIG_TSEC1_NAME "owt0"
|
||||
#define CONFIG_TSEC2_NAME "owt1"
|
||||
#define CONFIG_TSEC3_NAME "peer"
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC3_PHYIDX 0
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 3
|
||||
#define TSEC3_PHY_ADDR 4
|
||||
#define TSEC3_PHY_ADDR_CPUA 4
|
||||
#define TSEC3_PHY_ADDR_CPUB 5
|
||||
|
||||
/* PCI-E dual-port E1000 (external ethernet ports) */
|
||||
#define CONFIG_E1000
|
||||
#define CONFIG_E1000_SPI
|
||||
#define CONFIG_E1000_SPI_GENERIC
|
||||
#define CONFIG_CMD_E1000
|
||||
|
||||
/* We need the SPI infrastructure to poke the E1000's EEPROM */
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_SPI_X
|
||||
#define CONFIG_CMD_SPI
|
||||
#define MAX_SPI_BYTES 32
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* USB Thumbdrive Device Support */
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/* Partition and Filesystem support */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* Command line configuration. */
|
||||
#define CONFIG_CMDLINE_EDITING /* Enable command editing */
|
||||
#define CONFIG_COMMAND_HISTORY /* Enable command history */
|
||||
#define CONFIG_AUTO_COMPLETE /* Enable command completion */
|
||||
#define CONFIG_SYS_LONGHELP /* Enable detailed command help */
|
||||
#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */
|
||||
#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */
|
||||
#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */
|
||||
#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */
|
||||
|
||||
/* A little extra magic here for the prompt */
|
||||
#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
|
||||
#ifndef __ASSEMBLY__
|
||||
const char *hww1u1a_get_ps1(void);
|
||||
#endif
|
||||
|
||||
/* Include a bunch of default commands we probably want */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
/* Other helpful shell-like commands */
|
||||
#define CONFIG_MD5
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_CMD_MD5SUM
|
||||
#define CONFIG_CMD_SHA1
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* Image manipulation and booting */
|
||||
|
||||
/* We use the OpenFirmware-esque "Flattened Device Tree" */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */
|
||||
|
||||
/* This is the default address for commands with an optional address arg */
|
||||
#define CONFIG_LOADADDR 100000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000
|
||||
|
||||
/* Test memory starting from the default load address to just below 2GB */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR
|
||||
#define CONFIG_SYS_MEMTEST_END 0x7f000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 20
|
||||
#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
|
||||
#define CONFIG_BOOTARGS ""
|
||||
#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
|
||||
|
||||
/* Extra environment parameters */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
|
||||
"perf_mode=performance\0" \
|
||||
"hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
|
||||
"usb1:dr_mode=host,phy_type=ulpi\0" \
|
||||
"flkernel=0xe8020000\0" \
|
||||
"flinitramfs=0xe8800000\0" \
|
||||
"fldevicetree=0xeff20000\0" \
|
||||
"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \
|
||||
"flboot=run preboot; run flbootm\0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user