configs: move CONFIG_SPL_TEXT_BASE to Kconfig
Moved CONFIG_SPL_TEXT_BASE to common/spl/Kconfig and migrate existing values. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Re-run migration] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
committed by
Tom Rini
parent
d168bcb6fe
commit
f89d6133ee
@@ -17,7 +17,6 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#else
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -24,7 +24,6 @@
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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@@ -32,7 +32,6 @@
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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@@ -33,7 +33,6 @@
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_NAND_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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@@ -16,7 +16,6 @@
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#ifdef CONFIG_SDCARD
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_SPL_MAX_SIZE (96 * 1024)
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
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@@ -39,7 +38,6 @@
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_SPL_MAX_SIZE (96 * 1024)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
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@@ -62,7 +60,6 @@
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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@@ -88,7 +85,6 @@
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_NAND_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
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@@ -13,7 +13,6 @@
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#ifdef CONFIG_SDCARD
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_MAX_SIZE (128 * 1024)
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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@@ -32,7 +31,6 @@
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_MAX_SIZE (128 * 1024)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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@@ -67,7 +65,6 @@
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 4096
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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@@ -29,7 +29,6 @@
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -32,7 +32,6 @@
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -21,7 +21,6 @@
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#endif
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#ifdef CONFIG_SPL_BUILD
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@@ -36,7 +36,6 @@
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -30,7 +30,6 @@
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -21,7 +21,6 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#else
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -21,7 +21,6 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#else
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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@@ -43,7 +43,6 @@
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"usb_pgood_delay=2000\0"
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/* SPL support */
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#define CONFIG_SPL_TEXT_BASE 0xe6300000
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#define CONFIG_SPL_STACK 0xe6340000
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#define CONFIG_SPL_MAX_SIZE 0x4000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
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@@ -218,7 +218,6 @@
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GENERATED_GBL_DATA_SIZE)
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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@@ -189,8 +189,6 @@
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#define CONFIG_ENV_ADDR 0x260000
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/* Defines for SPL */
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#undef CONFIG_SPL_TEXT_BASE
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#define CONFIG_SPL_TEXT_BASE 0x40200000
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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@@ -35,7 +35,6 @@
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#define CONFIG_POWER_TPS62362
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/* SPL defines. */
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#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
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(128 << 20))
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@@ -19,11 +19,6 @@
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#define CONFIG_SYS_SDRAM_BASE1 0x880000000
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/* SPL Loader Configuration */
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#ifdef CONFIG_TARGET_AM654_A53_EVM
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#define CONFIG_SPL_TEXT_BASE 0x80080000
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#else
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#define CONFIG_SPL_TEXT_BASE 0x41c00000
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#endif
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#ifdef CONFIG_SYS_K3_SPL_ATF
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
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@@ -27,7 +27,6 @@
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*/
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_MAX_SIZE 2048
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#define CONFIG_SPL_TEXT_BASE 0xA0000000
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/* NAND boot config */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@@ -96,7 +96,6 @@
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x010000
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#define CONFIG_SPL_STACK 0x310000
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@@ -133,7 +133,6 @@
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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/* SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x6000
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#define CONFIG_SPL_STACK 0x308000
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@@ -106,7 +106,6 @@
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
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/* SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x6000
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#define CONFIG_SPL_STACK 0x308000
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@@ -41,7 +41,6 @@
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* Y-MODEM to load u-boot.img, when booted over UART. We must also include
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* the scratch space that U-Boot uses in SRAM.
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*/
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#define CONFIG_SPL_TEXT_BASE 0x402F0400
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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@@ -18,8 +18,6 @@
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_OFFSET 0x003f8000
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#define CONFIG_SPL_TEXT_BASE 0xfffd0000
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#define BOOT_DEVICE_SPI 10
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#define CONFIG_SPL_BOARD_LOAD_IMAGE
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@@ -59,7 +59,6 @@
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/* SPL */
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#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
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#define CONFIG_SPL_TEXT_BASE 0xf4000a00
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#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
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#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
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@@ -73,7 +73,6 @@
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/* Defines for SPL */
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#define CONFIG_SPL_SIZE (140 << 10)
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#define CONFIG_SPL_TEXT_BASE 0x40000030
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
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@@ -232,7 +232,6 @@
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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@@ -119,7 +119,6 @@
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"fi;"
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/* SPL defines. */
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#define CONFIG_SPL_TEXT_BASE 0x40300350
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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@@ -76,10 +76,8 @@
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#define CONFIG_SPL_SIZE (160 << 10)
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#if defined(CONFIG_SECURED_MODE_IMAGE)
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#define CONFIG_SPL_TEXT_BASE 0x40002614
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
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#else
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#define CONFIG_SPL_TEXT_BASE 0x40000030
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
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#endif
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@@ -103,7 +103,6 @@
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SZ_4M, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
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#define CONFIG_SPL_STACK (SZ_16K)
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@@ -273,7 +273,6 @@
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CONFIG_SYS_MALLOC_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SPL_STACK 0x8001ff00
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#define CONFIG_SPL_TEXT_BASE 0x80000000
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#define CONFIG_SPL_MAX_FOOTPRINT 32768
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#define CONFIG_SPL_PAD_TO 32768
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#endif
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@@ -60,7 +60,6 @@
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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@@ -55,7 +55,6 @@
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/* Defines for SPL */
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#define CONFIG_SPL_SIZE (140 << 10)
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#define CONFIG_SPL_TEXT_BASE 0x40000030
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
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@@ -71,7 +71,6 @@
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/* Defines for SPL */
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#define CONFIG_SPL_SIZE (140 << 10)
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#define CONFIG_SPL_TEXT_BASE 0x40000030
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
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@@ -70,7 +70,6 @@
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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@@ -157,7 +157,6 @@
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* SPL specific defines
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*/
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/* SPL will be executed at offset 0 */
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#define CONFIG_SPL_TEXT_BASE 0x00000000
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/* SPL will use SRAM as stack */
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#define CONFIG_SPL_STACK 0x0000FFF8
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@@ -154,9 +154,6 @@
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/* Defines for SPL */
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#undef CONFIG_SPL_TEXT_BASE
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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@@ -78,7 +78,6 @@
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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@@ -15,7 +15,6 @@
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* SPL
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*/
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#define CONFIG_SPL_TEXT_BASE 0xffff0000
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#define CONFIG_SPL_MAX_SIZE 0x0000fff0
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#define CONFIG_SPL_STACK 0x00020000
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#define CONFIG_SPL_BSS_START_ADDR 0x00020000
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@@ -17,8 +17,6 @@
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#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
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#define CONFIG_SPL_TEXT_BASE 0x02023400
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#define CONFIG_IRAM_STACK 0x02050000
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
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@@ -17,11 +17,6 @@
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#define CONFIG_VAR_SIZE_SPL
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#ifdef CONFIG_VAR_SIZE_SPL
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#define CONFIG_SPL_TEXT_BASE 0x02024410
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#else
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#define CONFIG_SPL_TEXT_BASE 0x02024400
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#endif
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#define CONFIG_IRAM_TOP 0x02074000
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#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
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@@ -50,7 +50,6 @@
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#define CONFIG_ENV_SIZE (64 << 10)
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/* SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x7000
|
||||
#define CONFIG_SPL_STACK 0x308000
|
||||
|
||||
|
||||
@@ -38,7 +38,6 @@
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
#define CONFIG_SPL_STACK 0xe6340000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x4000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
|
||||
|
||||
@@ -87,7 +87,6 @@
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_SIZE (140 << 10)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40000030
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
|
||||
|
||||
@@ -20,7 +20,6 @@
|
||||
* and some padding thus 'our' max size is really 0x00908000 - 0x00918000
|
||||
* or 64KB
|
||||
*/
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00908000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_STACK 0x0091FFB8
|
||||
/*
|
||||
|
||||
@@ -21,7 +21,6 @@
|
||||
* and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
|
||||
* 64KB is more then enough for the SPL.
|
||||
*/
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00911000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_STACK 0x00946BB8
|
||||
/*
|
||||
|
||||
@@ -13,7 +13,6 @@
|
||||
#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x7E1000
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
|
||||
@@ -10,7 +10,6 @@
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
|
||||
@@ -212,7 +212,6 @@
|
||||
CONFIG_SYS_MALLOC_LEN)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SPL_STACK 0x8001ff00
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x20000
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT 32768
|
||||
|
||||
|
||||
@@ -70,7 +70,6 @@
|
||||
* SPL
|
||||
*/
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40300000
|
||||
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
|
||||
|
||||
@@ -38,7 +38,6 @@
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
#define CONFIG_SPL_STACK 0xe6340000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x4000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
|
||||
|
||||
@@ -39,7 +39,6 @@
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
#define CONFIG_SPL_STACK 0xe6340000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x4000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
|
||||
|
||||
@@ -69,7 +69,6 @@
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
||||
#define CONFIG_SPL_STACK 0x1001d000
|
||||
#define CONFIG_SPL_PAD_TO 0x1c000
|
||||
|
||||
@@ -51,7 +51,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
||||
#define CONFIG_SPL_STACK 0x1001d000
|
||||
#define CONFIG_SPL_PAD_TO 0x1c000
|
||||
@@ -67,7 +66,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
||||
#define CONFIG_SPL_STACK 0x1001d000
|
||||
#define CONFIG_SPL_PAD_TO 0x1c000
|
||||
|
||||
@@ -74,7 +74,6 @@
|
||||
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
||||
#endif /* ifdef CONFIG_SECURE_BOOT */
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
||||
#define CONFIG_SPL_STACK 0x1001d000
|
||||
#define CONFIG_SPL_PAD_TO 0x1c000
|
||||
|
||||
@@ -64,7 +64,6 @@
|
||||
/* SD boot SPL */
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x17000
|
||||
#define CONFIG_SPL_STACK 0x1001e000
|
||||
#define CONFIG_SPL_PAD_TO 0x1d000
|
||||
@@ -92,7 +91,6 @@
|
||||
/* NAND SPL */
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define CONFIG_SPL_PBL_PAD
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
||||
#define CONFIG_SPL_STACK 0x1001d000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
||||
@@ -63,7 +63,6 @@
|
||||
|
||||
/* SD boot SPL */
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
|
||||
#define CONFIG_SPL_STACK 0x10020000
|
||||
#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
|
||||
@@ -89,7 +88,6 @@
|
||||
|
||||
#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
|
||||
#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x1f000
|
||||
#define CONFIG_SPL_STACK 0x10020000
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
@@ -114,7 +112,6 @@
|
||||
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
|
||||
#define CONFIG_SPL_STACK 0x1001f000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
||||
@@ -228,7 +228,6 @@ unsigned long long get_qixis_addr(void);
|
||||
#define CONFIG_SPL_MAX_SIZE 0x16000
|
||||
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x1800a000
|
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
|
||||
|
||||
@@ -208,7 +208,6 @@ unsigned long long get_qixis_addr(void);
|
||||
#define CONFIG_SPL_MAX_SIZE 0x16000
|
||||
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x1800a000
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
|
||||
|
||||
@@ -175,7 +175,6 @@
|
||||
* NAND SPL
|
||||
*/
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x70008000
|
||||
#define CONFIG_SPL_PAD_TO 0x8000
|
||||
#define CONFIG_SPL_STACK 0x70004000
|
||||
|
||||
|
||||
@@ -58,7 +58,6 @@
|
||||
|
||||
/* SPL */
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
||||
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
||||
|
||||
@@ -246,7 +246,6 @@
|
||||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_ECC
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
|
||||
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
|
||||
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
|
||||
|
||||
|
||||
@@ -33,7 +33,6 @@
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_STACK 0x106000
|
||||
#define CONFIG_SPL_TEXT_BASE 0x201000
|
||||
#define CONFIG_SPL_MAX_SIZE SZ_64K
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K
|
||||
#define CONFIG_SPL_PAD_TO 0x10000
|
||||
|
||||
@@ -25,8 +25,6 @@
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_MAX_SIZE 2048
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x87dc0000
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
@@ -80,7 +80,6 @@
|
||||
* As for the SPL, we must avoid the first 4 KiB as well, but we load the
|
||||
* IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
|
||||
*/
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00001000
|
||||
|
||||
/* U-Boot general configuration */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
|
||||
|
||||
@@ -17,8 +17,6 @@
|
||||
* We are only ever GP parts and will utilize all of the "downloaded image"
|
||||
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
|
||||
*/
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
||||
@@ -22,8 +22,6 @@
|
||||
* We are only ever GP parts and will utilize all of the "downloaded image"
|
||||
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
|
||||
*/
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
||||
@@ -15,8 +15,6 @@
|
||||
* We are only ever GP parts and will utilize all of the "downloaded image"
|
||||
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
|
||||
*/
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000
|
||||
|
||||
#define CONFIG_REVISION_TAG 1
|
||||
|
||||
|
||||
@@ -19,8 +19,6 @@
|
||||
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
|
||||
* order to allow for BCH8 to fit in.
|
||||
*/
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
||||
@@ -11,8 +11,6 @@
|
||||
* We are only ever GP parts and will utilize all of the "downloaded image"
|
||||
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
|
||||
*/
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000
|
||||
|
||||
/* call misc_init_r */
|
||||
|
||||
|
||||
@@ -270,7 +270,6 @@
|
||||
CONFIG_SYS_MALLOC_LEN)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SPL_STACK 0x8001ff00
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80000000
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT 32768
|
||||
#define CONFIG_SPL_PAD_TO 32768
|
||||
#endif
|
||||
|
||||
@@ -44,7 +44,6 @@
|
||||
|
||||
/* MMC SPL */
|
||||
#define COPY_BL2_FNPTR_ADDR 0x02020030
|
||||
#define CONFIG_SPL_TEXT_BASE 0x02021410
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x40007000\0" \
|
||||
|
||||
@@ -137,7 +137,6 @@
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
|
||||
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
|
||||
@@ -156,7 +155,6 @@
|
||||
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
|
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
|
||||
@@ -188,7 +186,6 @@
|
||||
#define CONFIG_SPL_INIT_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_TEXT_BASE 0xff800000
|
||||
#define CONFIG_SPL_MAX_SIZE 4096
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
|
||||
|
||||
@@ -21,8 +21,6 @@
|
||||
*
|
||||
* Tweak the SPL text base address to avoid this.
|
||||
*/
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00909000
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
@@ -104,7 +104,6 @@
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x010000
|
||||
#define CONFIG_SPL_STACK 0x310000
|
||||
|
||||
|
||||
@@ -87,7 +87,6 @@
|
||||
128 * 1024, 0x1000)
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x010000
|
||||
#define CONFIG_SPL_STACK 0x310000
|
||||
|
||||
|
||||
@@ -43,7 +43,6 @@
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
#define CONFIG_SPL_STACK 0xe6340000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x4000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
|
||||
|
||||
@@ -35,8 +35,6 @@
|
||||
|
||||
/* SPI is not supported */
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0xfffd0000
|
||||
|
||||
#define BOOT_DEVICE_SPI 10
|
||||
|
||||
#define CONFIG_SPL_BOARD_LOAD_IMAGE
|
||||
|
||||
@@ -19,7 +19,6 @@
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x60800800
|
||||
#define CONFIG_SPL_STACK 0x10081fff
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10081000
|
||||
|
||||
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
|
||||
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
|
||||
|
||||
@@ -26,7 +26,6 @@
|
||||
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
|
||||
#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10080800
|
||||
/* spl size 32kb sram - 2kb bootrom */
|
||||
#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
|
||||
#define CONFIG_ROCKCHIP_SERIAL 1
|
||||
|
||||
@@ -20,7 +20,6 @@
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x60800800
|
||||
#define CONFIG_SPL_STACK 0x10088000
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10081000
|
||||
|
||||
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
|
||||
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
|
||||
|
||||
@@ -23,11 +23,6 @@
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00800800
|
||||
#define CONFIG_SPL_STACK 0xff718000
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
|
||||
# define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#else
|
||||
# define CONFIG_SPL_TEXT_BASE 0xff704000
|
||||
#endif
|
||||
|
||||
/* RAW SD card / eMMC locations. */
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
|
||||
|
||||
@@ -27,7 +27,6 @@
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00280000
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x40000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x400000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
|
||||
|
||||
@@ -19,7 +19,6 @@
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00800800
|
||||
#define CONFIG_SPL_STACK 0xff8effff
|
||||
#define CONFIG_SPL_TEXT_BASE 0xff8c2000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
|
||||
/* BSS setup */
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
|
||||
|
||||
@@ -56,7 +56,6 @@
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x200000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -52,7 +52,6 @@
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x200000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -47,7 +47,6 @@
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x200000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -58,7 +58,6 @@
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x18000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -72,7 +72,6 @@
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x18000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -36,7 +36,6 @@
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x200000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x18000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -36,7 +36,6 @@
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x200000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x18000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
@@ -86,7 +86,6 @@
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x402F0400
|
||||
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
|
||||
|
||||
@@ -43,7 +43,6 @@
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
#define CONFIG_SPL_STACK 0xe6340000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x4000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
|
||||
|
||||
@@ -174,7 +174,6 @@
|
||||
#endif
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#define CONFIG_SPL_MAX_SIZE (SZ_4K)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define COPY_BL2_FNPTR_ADDR 0x00002488
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x02021410
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
||||
@@ -64,7 +64,6 @@
|
||||
* SPL
|
||||
*/
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000
|
||||
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
|
||||
|
||||
@@ -197,7 +197,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
|
||||
* 0xFFE3_FFFF ...... End of SRAM (top)
|
||||
*/
|
||||
#ifndef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
|
||||
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
@@ -197,7 +197,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
|
||||
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
|
||||
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
|
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
|
||||
|
||||
@@ -67,7 +67,6 @@
|
||||
/* For SPL */
|
||||
#ifdef CONFIG_SUPPORT_SPL
|
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_SPL_LEN 0x00008000
|
||||
#define CONFIG_SYS_UBOOT_START 0x080083FD
|
||||
|
||||
@@ -59,7 +59,6 @@
|
||||
/* SPL support */
|
||||
#ifdef CONFIG_SPL
|
||||
/* BOOTROM load address */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x2FFC2500
|
||||
/* SPL use DDR */
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0xC0200000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user