ram: k3-ddrss: Introduce ECC Functionality for full memory space
Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach
Tom Rini
parent
71eb527476
commit
f861ce90ca
@ -6,9 +6,12 @@
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*/
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#include <common.h>
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#include <config.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <fdt_support.h>
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#include <ram.h>
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#include <hang.h>
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#include <log.h>
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@ -30,6 +33,19 @@
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#define DDRSS_V2A_R1_MAT_REG 0x0020
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#define DDRSS_ECC_CTRL_REG 0x0120
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#define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0)
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#define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1)
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#define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2)
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#define DDRSS_ECC_CTRL_REG_WR_ALLOC BIT(4)
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#define DDRSS_ECC_R0_STR_ADDR_REG 0x0130
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#define DDRSS_ECC_R0_END_ADDR_REG 0x0134
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#define DDRSS_ECC_R1_STR_ADDR_REG 0x0138
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#define DDRSS_ECC_R1_END_ADDR_REG 0x013c
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#define DDRSS_ECC_R2_STR_ADDR_REG 0x0140
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#define DDRSS_ECC_R2_END_ADDR_REG 0x0144
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#define DDRSS_ECC_1B_ERR_CNT_REG 0x0150
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#define SINGLE_DDR_SUBSYSTEM 0x1
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#define MULTI_DDR_SUBSYSTEM 0x2
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@ -102,6 +118,13 @@ struct k3_msmc {
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enum emif_active active;
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};
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#define K3_DDRSS_MAX_ECC_REGIONS 3
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struct k3_ddrss_ecc_region {
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u32 start;
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u32 range;
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};
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struct k3_ddrss_desc {
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struct udevice *dev;
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void __iomem *ddrss_ss_cfg;
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@ -119,6 +142,9 @@ struct k3_ddrss_desc {
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lpddr4_obj *driverdt;
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lpddr4_config config;
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lpddr4_privatedata pd;
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struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
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u64 ecc_reserved_space;
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bool ti_ecc_enabled;
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};
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struct reginitdata {
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@ -329,6 +355,14 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
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}
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ddrss->ddrss_ctrl_mmr = (void *)reg;
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reg = dev_read_addr_name(dev, "ss_cfg");
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if (reg == FDT_ADDR_T_NONE) {
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dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
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ddrss->ddrss_ss_cfg = NULL;
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} else {
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ddrss->ddrss_ss_cfg = (void *)reg;
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}
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ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
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if (ret) {
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dev_err(dev, "power_domain_get() failed: %d\n", ret);
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@ -372,6 +406,8 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
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if (ret)
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dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
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ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");
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return ret;
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}
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@ -513,6 +549,60 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
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}
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}
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static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size)
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{
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writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
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writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
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}
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static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word)
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{
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int i;
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printf("ECC is enabled, priming DDR which will take several seconds.\n");
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for (i = 0; i < (size / 4); i++)
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addr[i] = word;
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}
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static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
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{
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fdtdec_setup_mem_size_base_lowest();
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ddrss->ecc_reserved_space = gd->ram_size;
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do_div(ddrss->ecc_reserved_space, 9);
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/* Round to clean number */
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ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space));
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}
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static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
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{
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u32 ecc_region_start = ddrss->ecc_regions[0].start;
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u32 ecc_range = ddrss->ecc_regions[0].range;
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u32 base = (u32)ddrss->ddrss_ss_cfg;
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u32 val;
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/* Only Program region 0 which covers full ddr space */
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k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range);
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/* Enable ECC, RMW, WR_ALLOC */
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writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
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DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
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/* Preload ECC Mem region with 0's */
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k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range,
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0x00000000);
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/* Clear Error Count Register */
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writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
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/* Enable ECC Check */
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val = readl(base + DDRSS_ECC_CTRL_REG);
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val |= DDRSS_ECC_CTRL_REG_ECC_CK;
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writel(val, base + DDRSS_ECC_CTRL_REG);
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}
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static int k3_ddrss_probe(struct udevice *dev)
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{
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int ret;
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@ -547,9 +637,52 @@ static int k3_ddrss_probe(struct udevice *dev)
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k3_lpddr4_start(ddrss);
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if (ddrss->ti_ecc_enabled) {
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if (!ddrss->ddrss_ss_cfg) {
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printf("%s: ss_cfg is required if ecc is enabled but not provided.",
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__func__);
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return -EINVAL;
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}
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k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
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/* Always configure one region that covers full DDR space */
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ddrss->ecc_regions[0].start = gd->ram_base;
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ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space;
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k3_ddrss_lpddr4_ecc_init(ddrss);
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}
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return ret;
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}
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int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
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{
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struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
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u64 start[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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int bank;
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if (ddrss->ecc_reserved_space == 0)
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return 0;
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for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
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if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) {
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ddrss->ecc_reserved_space -= bd->bi_dram[bank].size;
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bd->bi_dram[bank].size = 0;
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} else {
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bd->bi_dram[bank].size -= ddrss->ecc_reserved_space;
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break;
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}
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}
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start[bank] = bd->bi_dram[bank].start;
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size[bank] = bd->bi_dram[bank].size;
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}
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return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
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}
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static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
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{
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return 0;
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16
include/k3-ddrss.h
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16
include/k3-ddrss.h
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Texas Instruments' K3 DDRSS Driver
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*
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* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#ifndef _K3_DDRSS_
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#define _K3_DDRSS_
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struct udevice;
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int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd);
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#endif
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