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Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

Browse Source 
- Misc Kconfig cleanups (Chris & Pali)
- turris_omnia: Fix hangup in debug UART (this introduces
  TPL/SPL_DEBUG_UART_BASE) Pali
- mvebu: uDPU: include fixed-phy support (Robert)
- pinctrl: probe pinctrl drivers during post-bind (Robert)
This commit is contained in:
Tom Rini 2022-05-18 08:41:13 -04:00
commit f83bd23e2a
23 changed files with 92 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/Kconfig
View File

@ -401,6 +401,12 @@ config SYS_ARM_CACHE_WRITEALLOC
write is performed.
endchoice
config ARCH_VERY_EARLY_INIT
bool
config SPL_ARCH_VERY_EARLY_INIT
bool
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help

5
arch/arm/lib/crt0.S
View File

@ -90,6 +90,11 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */
ENTRY(_main)
/* Call arch_very_early_init before initializing C runtime environment. */
#if CONFIG_IS_ENABLED(ARCH_VERY_EARLY_INIT)
bl arch_very_early_init
#endif
/*
* Set up initial C runtime environment and call board_init_f(0).
*/

5
arch/arm/mach-mvebu/Kconfig
View File

@ -16,10 +16,7 @@ config ARMADA_32BIT
select SUPPORT_SPL
select TRANSLATION_OFFSET
select SPL_SYS_NO_VECTOR_TABLE if SPL
config ARMADA_64BIT
bool
select ARM64
select ARCH_VERY_EARLY_INIT
# ARMv7 SoCs...
config ARMADA_375

1
arch/arm/mach-mvebu/Makefile
View File

@ -21,6 +21,7 @@ else # CONFIG_ARCH_KIRKWOOD
obj-y = cpu.o
obj-y += dram.o
obj-y += lowlevel.o
obj-$(CONFIG_DM_RESET) += system-controller.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o

31
arch/arm/mach-mvebu/cpu.c
View File

@ -413,20 +413,7 @@ static void update_sdram_window_sizes(void)
}
}
void mmu_disable(void)
{
asm volatile(
"mrc p15, 0, r0, c1, c0, 0\n"
"bic r0, #1\n"
"mcr p15, 0, r0, c1, c0, 0\n");
}
#ifdef CONFIG_ARCH_CPU_INIT
static void set_cbar(u32 addr)
{
asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
}
#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
#define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
#define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
@ -476,24 +463,6 @@ int arch_cpu_init(void)
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
/*
* Only with disabled MMU its possible to switch the base
* register address on Armada 38x. Without this the SDRAM
* located at >= 0x4000.0000 is also not accessible, as its
* still locked to cache.
*/
mmu_disable();
/* Linux expects the internal registers to be at 0xf1000000 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
/*
* From this stage on, the SoC detection is working. As we have
* configured the internal register base to the value used
* in the macros / defines in the U-Boot header (soc.h).
*/
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
/*
* To fully release / unlock this area from cache, we need

27
arch/arm/mach-mvebu/lowlevel.S Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#include <config.h>
#include <linux/linkage.h>
ENTRY(arch_very_early_init)
#ifdef CONFIG_ARMADA_38X
/*
* Only with disabled MMU its possible to switch the base
* register address on Armada 38x. Without this the SDRAM
* located at >= 0x4000.0000 is also not accessible, as its
* still locked to cache.
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, #1
mcr p15, 0, r0, c1, c0, 0
#endif
/* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */
ldr r0, =SOC_REGS_PHY_BASE
ldr r1, =INTREG_BASE_ADDR_REG
str r0, [r1]
add r0, r0, #0xC000
mcr p15, 4, r0, c15, c0
bx lr
ENDPROC(arch_very_early_init)

4
cmd/mvebu/Kconfig
View File

@ -9,6 +9,8 @@ config CMD_MVEBU_BUBT
For details about bubt command please see the documentation
in doc/mvebu/cmd/bubt.txt
if CMD_MVEBU_BUBT
choice
prompt "Flash for image"
default MVEBU_SPI_BOOT
@ -49,6 +51,8 @@ config MVEBU_UBOOT_DFLT_NAME
This option should contain a default file name to be used with
MVEBU "bubt" command if the source file name is omitted
endif
config CMD_MVEBU_COMPHY_RX_TRAINING
bool "mvebu_comphy_rx_training"
depends on ARMADA_8K

3
configs/clearfog_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -66,6 +66,7 @@ CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/controlcenterdc_defconfig
View File

@ -16,7 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -84,6 +84,7 @@ CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
CONFIG_SCSI_AHCI_PLAT=y
CONFIG_SYS_SCSI_MAX_SCSI_ID=2
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/db-88f6820-amc_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -70,6 +70,7 @@ CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/db-88f6820-gp_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -66,6 +66,7 @@ CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/db-mv784mp-gp_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -68,6 +68,7 @@ CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/ds414_defconfig
View File

@ -19,7 +19,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -68,6 +68,7 @@ CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/helios4_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -67,6 +67,7 @@ CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/maxbcm_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -48,6 +48,7 @@ CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_MII=y
CONFIG_MVMDIO=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

3
configs/theadorable_debug_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_MEM_TOP_HIDE=0x80000
CONFIG_SYS_LOAD_ADDR=0x800000
@ -74,6 +74,7 @@ CONFIG_MVMDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_MVEBU=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

1
configs/turris_mox_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_BUTTON=y

4
configs/turris_omnia_defconfig
View File

@ -18,7 +18,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_DEBUG_UART=y
@ -68,6 +68,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@34000"
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_PCI=y
CONFIG_AHCI_MVEBU=y
@ -93,6 +94,7 @@ CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y
CONFIG_RTC_ARMADA38X=y
CONFIG_SCSI=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

1
configs/uDPU_defconfig
View File

@ -70,6 +70,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVNETA=y

3
configs/x530_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_ENV_ADDR=0x100000
@ -72,6 +72,7 @@ CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y

7
drivers/pinctrl/pinctrl-uclass.c
View File

@ -402,6 +402,13 @@ static int __maybe_unused pinctrl_post_bind(struct udevice *dev)
{
const struct pinctrl_ops *ops = pinctrl_get_ops(dev);
/*
* Make sure that the pinctrl driver gets probed after binding
* as some pinctrl drivers also register the GPIO driver during
* probe, and if they are not probed GPIO-s are not registered.
*/
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
if (!ops) {
dev_dbg(dev, "ops is not set. Do not bind.\n");
return -EINVAL;

14
drivers/serial/Kconfig
View File

@ -508,6 +508,20 @@ config DEBUG_UART_BASE
A default should be provided by your board, but if not you will need
to use the correct value here.
config SPL_DEBUG_UART_BASE
hex "Base address of UART for SPL"
depends on SPL && DEBUG_UART
default DEBUG_UART_BASE
help
This is the base address of your UART for memory-mapped UARTs for SPL.
config TPL_DEBUG_UART_BASE
hex "Base address of UART for TPL"
depends on TPL && DEBUG_UART
default DEBUG_UART_BASE
help
This is the base address of your UART for memory-mapped UARTs for TPL.
config DEBUG_UART_CLOCK
int "UART input clock"
depends on DEBUG_UART

4
drivers/serial/ns16550.c
View File

@ -325,7 +325,7 @@ int ns16550_tstc(struct ns16550 *com_port)
static inline void _debug_uart_init(void)
{
struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
int baud_divisor;
/*
@ -360,7 +360,7 @@ static inline int NS16550_read_baud_divisor(struct ns16550 *com_port)
static inline void _debug_uart_putc(int ch)
{
struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
#ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED