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spi: synquacer: simplify tx completion checking

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There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Masahisa Kojima 2022-05-17 17:41:39 +09:00 committed by Tom Rini
parent de9f2c9c2e
commit f81aaa0b33
1 changed files with 4 additions and 6 deletions
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10
drivers/spi/spi-synquacer.c
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@ -45,6 +45,7 @@
#define RXF 0x20 #define RXF 0x20
#define RXE 0x24 #define RXE 0x24
#define RXC 0x28 #define RXC 0x28
#define TFES 1
#define TFLETE 4 #define TFLETE 4
#define TSSRS 6 #define TSSRS 6
#define RFMTE 5 #define RFMTE 5
@ -345,13 +346,10 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
if (priv->tx_words) { if (priv->tx_words) {
write_fifo(priv); write_fifo(priv);
} else { } else {
u32 len; /* wait for shifter to empty out */
while (!(readl(priv->base + TXF) & BIT(TFES)))
do { /* wait for shifter to empty out */
cpu_relax(); cpu_relax();
len = readl(priv->base + DMSTATUS);
len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
} while (tx_buf && len);
busy &= ~BIT(TXBIT); busy &= ~BIT(TXBIT);
} }
} }