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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Wolfgang Denk
2008-10-27 22:31:32 +01:00
parent 5deb8022c3 c2083e0e11
commit f8030519bb
37 changed files with 626 additions and 689 deletions
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4
cpu/mpc85xx/cpu.c
View File

@@ -134,6 +134,10 @@ int checkcpu (void)
puts("Unknown");
break;
}
if (PVR_MEM(pvr) == 0x03)
puts("MC");
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);

9
cpu/mpc85xx/ddr-gen3.c
View File

@@ -79,15 +79,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
/*
* 32-bit workaround for DDR2
* 32_BE
* For 8572 DDR1 erratum - DDR controller may enter illegal state
* when operatiing in 32-bit bus mode with 4-beat bursts,
* This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
#ifdef CONFIG_MPC8572
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg_2) & 0x80000) {
&& in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
u32 temp = in_be32(&ddr->debug_1);
out_be32(&ddr->debug_1, temp | 1);
}
#endif
/*
* 200 painful micro-seconds must elapse between

8
cpu/mpc85xx/release.S
View File

@@ -24,14 +24,18 @@
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
#endif
/* Enable branch prediction */
li r3,0x201
@@ -64,7 +68,11 @@ __secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
#ifdef CONFIG_E500MC
rlwinm r4,r0,27,27,31
#else
mr r4,r0
#endif
slwi r8,r4,5
add r10,r3,r8

6
cpu/mpc85xx/start.S
View File

@@ -163,8 +163,10 @@ _start_e500:
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
mtspr HID0,r0
#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
@@ -998,8 +1000,8 @@ trap_reloc:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)